5 Commits (1e0fed82f766d20fcdecc44903d35865a1f52719)

Author	SHA1	Message	Date
Rejeesh Kutty	50552ce7d6	adrv9371x- altera updates	2016-10-27 09:25:00 -04:00
Rejeesh Kutty	f752f0c9d7	a10soc- xcvr updates	2016-10-27 09:25:00 -04:00
Adrian Costina	e40311eee9	adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz	2016-09-29 09:14:37 +01:00
Adrian Costina	2d307d5f58	a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design	2016-09-24 10:06:35 +03:00
Adrian Costina	40c9fc92c1	a10soc: Switched to tcl flow	2016-09-08 11:31:06 +03:00