1df6178ab8
library: Update common Makefile
2017-01-31 16:44:32 +02:00
b14d740f87
M2K: initial commit
2017-01-31 16:43:40 +02:00
7387df9d13
util_var_fifo: Initial commit
2017-01-31 16:26:45 +02:00
b9c94f63a5
util_extract: Initial commit
2017-01-31 16:26:05 +02:00
6604cc7322
axi_logic_analyzer: Initial commit
2017-01-31 16:23:56 +02:00
9c975211da
axi_dac_interpolate: Initial commit
2017-01-31 16:22:49 +02:00
4a7232cbcb
axi_adc_decimate: Initial commit
2017-01-31 16:21:39 +02:00
35b97abc6d
axi_adc_trigger: Initial commit
2017-01-31 16:20:13 +02:00
fb945ac51c
axi_ad9963: Initial commit
2017-01-31 16:18:58 +02:00
d5af828b9c
Merge branch 'dev' into hdl_2016_r2
2017-01-30 17:10:05 +02:00
db924953bb
altera- warnings about init values
2017-01-30 10:01:28 -05:00
97d72d2f65
a10gx- xilinx/altera sync-up
2017-01-30 10:01:28 -05:00
b14e7fe4ee
daq3/kcu105- 1.25GSPS
2017-01-30 10:01:28 -05:00
eb8a3fff3c
axi_dmac: Set IP core name and description
...
Add a human readable name and descriptor for the AXI DMAC core.This string
will appear in various places e.g. like the IP catalog. This is a purely
cosmetic change.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-01-30 13:58:48 +01:00
3dd736fe8c
axi_dmac: Add identification register
...
Add a register to the AXI DMAC register map which functions has a
identification register. The register contains the unique value of "DMAC"
(0x444d4143) and allows software to identify whether the peripheral mapped
at a certain address is an axi_dmac peripheral.
This is useful for detecting cases where the specified address contains an
error or is incorrect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-01-30 13:58:48 +01:00
48ad24cdbe
enable partial reconfiguration mode
2017-01-27 09:26:53 -05:00
3f3a8bd267
library: forced ad_mem module to be implemented in BRAM for Xilinx devices
2017-01-25 18:12:04 +02:00
c8b638e182
ad9152- add prbs generators
2017-01-23 10:31:57 -05:00
be1328c55b
kcu105- added missing ethernet configurations
2017-01-23 10:14:09 -05:00
a2b2ebbed2
ad_lvds_in- ultrascale/ultrascale+ sim device mess
2017-01-21 20:54:21 -05:00
661413627f
daq3- round about way to avoid ip getting locked
2017-01-20 15:55:33 -05:00
afcd11da87
adxcvr- add parameters for xcvr config
2017-01-19 12:40:26 -05:00
746b97dd96
xilin/axi_adxcvr: Fix clock and reset nets[C
2017-01-19 15:46:16 +02:00
57bd6acd0f
library: Update make file
2017-01-19 15:27:31 +02:00
62792ddaed
adrv9371x: Change the axi_adxcvr cores addresses
...
Because the S_AXI interface of the axi_adxcvr core was infered
using the process adi_ip_properties, the interface address range
has changed from 4k to 64k. As a result, all the addresses of
the axi_adxcvr cores were changed and realigned.
2017-01-19 15:23:03 +02:00
d3ed417f49
axi_adxcvr: Update the packaging script to fix infer mm issues
...
- Change the clock and reset port name of the AXI slave interface
to s_axi_aclk and s_axi_aresetn. This way we can use the adi_ip_properties
process to infer the interface.
- Define an address space reference to the m_axi interface.
2017-01-19 15:16:04 +02:00
7a7a294865
axi_dmac: Fix memory map infer issues
...
Define an address space reference to the m_dest_axi and
m_src_axi interfaces.
2017-01-19 15:09:07 +02:00
a7bd4e6e82
scripts/adi_ip: Update the adi_ip_properties process
...
- Add a process, which automaticaly infer AXI memory mapped
interfaces (adi_ip_infer_mm_interfaces)
- Add missign line breaks to the 'set_propery supported_families'
command
- Fix the deletion of pre-infered memory maps
2017-01-19 15:06:47 +02:00
ecd152c90d
pzsdr1: ccbrk_cmos, fix clkdiv parameters
2017-01-18 12:04:04 +02:00
165ba76d9d
pzsdr1: Added FIFOs for DAC and ADC paths so that they work at l_clk or l_clk/2
2017-01-18 12:01:24 +02:00
319a883c00
pzsdr2: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
2017-01-18 12:00:10 +02:00
61afd106b5
util_clkdiv: Keep as valid only settings common for 7Series and Ultrascale
2017-01-18 11:56:24 +02:00
9344dd34dc
zcu102: Update project to include clkdiv
2017-01-16 14:47:31 +02:00
4dcad7e116
fmcomms2: zcu102, update clkdiv device parameter
2017-01-16 14:38:37 +02:00
61ee24f26a
util_clkdiv: Make the clock division parametrizable and changed C_SIM_DEVICE to SIM_DEVICE
2017-01-16 14:37:26 +02:00
b622b6592e
FMCOMMS5/ZCU102 : Merge from njpillitteri/hdl:dev
...
Pull request Dev #26
2017-01-13 14:47:16 +02:00
d2e7b6b635
fmcomms5: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
2017-01-13 14:18:59 +02:00
a36057679a
fmcomms2: Update Makefiles
2017-01-13 14:16:21 +02:00
15c5bc7012
fmcomms2: zcu102, changed clkdiv C_SIM_DEVICE parameter to ultrascale
2017-01-13 13:57:32 +02:00
b84325d43f
fmcomms2: take into consideration both adc_r1 and dac_r1 for clock division selection
2017-01-13 13:56:04 +02:00
4b2602437f
util_clkdiv: Added Ultrascale support and switch to BUFGMUX_CTRL for glitch free switching
2017-01-13 13:54:07 +02:00
f003b5b35a
fmcjesdadc1: Reduce SYSREF period
2017-01-12 16:10:45 +02:00
1f7d19688a
Update Makefile
2017-01-12 15:58:32 +02:00
b59549053c
scripts/adi_ip: Fix adi_ip_infer_interfaces process
...
This patch is a complementary fix of 8b8c37 patch. And fix
all the 'infer interface' issues.
The adi_ip_infer_interfaces process was renamed to
adi_ip_infer_streaming_interfaces. Now the process just do
what its name suggest.
Affected cores were axi_dmac, axi_spdif_rx, axi_spdif_tx, axi_i2s_adi
and axi_usb_fx3. All these cores scripts were updated.
2017-01-12 12:15:33 +02:00
e77428c50e
fmcomms2: Added FIFOs for DAC and ADC paths so that the path works at l_clk / 2 or l_clk /4
...
- removed ILA
2017-01-11 18:12:35 +02:00
9b29941c77
util_clkdiv: Add constraint file
2017-01-11 18:11:53 +02:00
37d54bb984
fmcjesdadc1/a5gt- max delay fit only
2017-01-04 16:04:19 -05:00
8b74e911b8
fmcjesdadc1/a5gt- qr to ddio max delay
2017-01-04 14:10:44 -05:00
e4e5b30ade
fmcadc5: Integrate ad_sysref_gen into the project
2017-01-03 13:52:39 +02:00
14ded4f123
fmcjeadadc1/a5soc- ad_sysref_gen updates
2016-12-22 15:59:45 -05:00
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
Lars-Peter Clausen
Nick Pillitteri