27bb69b44c
Add copyright and license to .sdc files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 10:41:40 +03:00
28c06d505f
Add/edit copyright and license for .v, .sv files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
db94628cc6
library & projects: Update Makefiles
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
1eb5f4985b
projects/common: Add build files templates carriers. Modified Quartus Versions
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The build files are available for the following carriers:
* intel: a10gx, a10soc, c5soc, de10nano, s10soc
* xilinx: coraz7s, kc705, kcu105, vc707, vc709,
vck190, vcu118, vcu128, vmk180,
zc702, zc706, zcu102, zed
* Added Makefiles, system_constr.sdc, system_qsys intel
* Added Makefiles, system_bd, system_constr xilinx
* de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0
according to last commit update
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-10-05 10:47:21 +03:00
6b94259a52
projects/common: Add system_top _project templates
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Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct code and modify according to guidelines
* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct/Add missing wrapper ports and iobufs
* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
ac701/system_top.v: Change top based on previous projects
* Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
projects/common: Modify templates to build without errors
* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
system_project: Added adi_board, adiobuf sourcing
system_top: Removed hdmi, i2c, fanpwm, spdif ports
according to base design
* c5soc: Added version settings
Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
Removed unnecessary ports
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Delete microzed vmk_es templates
* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-09-20 17:00:49 +03:00
72cf8f9b5d
projects/common: Add fmc connection files for every platform
2022-09-20 14:11:08 +03:00
0a3724e04c
s10soc: Update base desgin from ES to production, H-Tile version
2021-09-30 17:40:13 +03:00
5a3c3c878b
ad9213_dual_ebz: Initial commit
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Used ADF4377 SPI configuration CPOL/CPHA 1 for increasing the reliability of the level translators
ad9213_dual_ebz/s10soc: Redesign the address layout
avl_peripheral_mm_bridge 0x0000000 0x0001FFFF
* sys_gpio_in 0x00000000
* sys_gpio_out 0x00000020
* sys_spi 0x00000040
* sys_gpio_bd 0x000000D0
* sys_id 0x000000E0
avl_mm_bridge_0 0x00040000 0x0007FFFF
* ad9213_rx_0.phy_reconfig_0 0x00000000
* ad9213_rx_0.phy_reconfig_1 0x00002000
* ad9213_rx_0.phy_reconfig_2 0x00004000
* ad9213_rx_0.phy_reconfig_3 0x00006000
* ad9213_rx_0.phy_reconfig_4 0x00008000
* ad9213_rx_0.phy_reconfig_5 0x0000A000
* ad9213_rx_0.phy_reconfig_6 0x0000C000
* ad9213_rx_0.phy_reconfig_7 0x0000E000
* ad9213_rx_0.phy_reconfig_8 0x00010000
* ad9213_rx_0.phy_reconfig_9 0x00012000
* ad9213_rx_0.phy_reconfig_10 0x00014000
* ad9213_rx_0.phy_reconfig_11 0x00016000
* ad9213_rx_0.phy_reconfig_12 0x00018000
* ad9213_rx_0.phy_reconfig_13 0x0001A000
* ad9213_rx_0.phy_reconfig_14 0x0001C000
* ad9213_rx_0.phy_reconfig_15 0x0001E000
* ad9213_rx_0.link_pll_reconfig 0x00020000
avl_mm_bridge_1 0x00080000 0x000BFFFF
* ad9213_rx_1.phy_reconfig_0 0x00000000
* ad9213_rx_1.phy_reconfig_1 0x00002000
* ad9213_rx_1.phy_reconfig_2 0x00004000
* ad9213_rx_1.phy_reconfig_3 0x00006000
* ad9213_rx_1.phy_reconfig_4 0x00008000
* ad9213_rx_1.phy_reconfig_5 0x0000A000
* ad9213_rx_1.phy_reconfig_6 0x0000C000
* ad9213_rx_1.phy_reconfig_7 0x0000E000
* ad9213_rx_1.phy_reconfig_8 0x00010000
* ad9213_rx_1.phy_reconfig_9 0x00012000
* ad9213_rx_1.phy_reconfig_10 0x00014000
* ad9213_rx_1.phy_reconfig_11 0x00016000
* ad9213_rx_1.phy_reconfig_12 0x00018000
* ad9213_rx_1.phy_reconfig_13 0x0001A000
* ad9213_rx_1.phy_reconfig_14 0x0001C000
* ad9213_rx_1.phy_reconfig_15 0x0001E000
* ad9213_rx_1.link_pll_reconfig 0x00020000
Connected directly to the h2s_lw_axi_master
* ad9213_rx_0.link_reconfig 0x000C0000
* ad9213_rx_0.link_management 0x000C4000
* ad9213_rx_1.link_reconfig 0x000C8000
* ad9213_rx_1.link_management 0x000CC000
* axi_ad9213_0.s_axi 0x000D0000
* axi_ad9213_1.s_axi 0x000D1000
* axi_ad9213_dma_0.s_axi 0x000D2000
* axi_ad9213_dma_1.s_axi 0x000D3800
2021-09-30 17:40:13 +03:00
8acf0296af
s10soc:ad_cpu_interconnect: Add an avl_address_width attribute
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The default address space for a new bridge is 256 Kbytes. Add an
avl_address_width attribute to the ad_cpu_interoconnect porecess to
define other address space sizes if needed.
The avl_peripheral_mm_bridge will have an 128 Kbyte address space from
address 0x0000.
2021-09-30 17:40:13 +03:00
230c579339
common/s10soc: Input ports do not have a current strength property
2020-09-25 12:56:14 +03:00
61ece1f1e9
s10soc: Insert an additional bridge between DMA and HPS
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Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
2020-09-09 14:15:37 +03:00
91b199a907
s10soc: Add new feature for ad_cpu_interconnect
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If we have a lot of peripherals connected to the CPU's memory interface,
the generated interconnect can grow to much decreasing the timing
margin.
One solution is to group the peripherals by its interface types and
functions and use bridges to connect them to the memory interface.
This commit adds the possibility to insert an Avalon Memory Mapped
bridge when we create the connection between the peripheral and CPU.
Should be used just with Avalaon Memory Mapped interfaces.
2020-09-09 14:15:37 +03:00
f9c4283f45
stratix10soc: Initial commit of base design
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Note: Currently we have a engineering sample version 2 board.
2020-09-09 14:15:37 +03:00
Iulia Moldovan
laurent-19
AndrDragomir
Adrian Costina
Istvan Csomortani