Commit Graph

5 Commits (1cac2d82e1eab7cf8688d08a0d711a986e69150f)

Author SHA1 Message Date
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Istvan Csomortani f624d5df40 intel_mem_asym: Update the interface definitions
The ram_2port IP has different interface names in Quartus PRO and
Quartus Standard.

Update the interface names for the support Quartus PRO.
2020-08-11 10:14:18 +03:00
Istvan Csomortani 2f0dbe6151 intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00