The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.
Projects which use spi_engine.tcl will be updated to account for
these changes.
- Quartus version was updated
- the start_n output port was deteled from system_top.v
- the ""mixed_port_feed_through_mode" parameter of RAM can not have value "old"" warning was disabled
- update Makefile copyright year
Signed-off-by: Paul Pop <paul.pop@analog.com>
bug:
say "make LVDS_CMOS_N=0"
- will set ad_project_dir as LVDSCMOSN0
- will then set system_qip_file as LVDSCMOSN0/system_bd/synthesis/system_bd.qip
- build error reveals system_bd can't be found
- maybe due to setting ad_project_dir as a relative file path
fix:
- set ad_project_dir as an absolute file path
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
If the sampling clock is lower than dclk*number_of_active_lines*32 the interface should wait for the next adc_ready signal to reset the counter.
The adc_valid_p signal should be set high just for a clock period after the sample was captured.
- Issue introduced by commit 173f4a83d4
- When IODELAY_ENABLE was inserted in axi_adrv9001_if for adrv9001_rx (Xilinx instance),
for Intel instance (intel/adrv9001_rx.v) was omitted and caused a build error for
adrv9001/a10soc
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Replaced the existing axi_tdd with the new version
* Added DEFAULT_POLARITY synth parameter and RO register
* Added TDD_STATUS register
* Added TDD_SYNC_RST feature
* Used the asy_ prefix for signals which are not synced
* Added logic to force the state from ARMED to RUNNING when startup_delay=0
* Added feature to finish the burst when the module is disabled before its completion
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.
Note that the 'JESD' and 'LANE' words from the parameter names are stripped.
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
In ad_xcvrcon procedure from adi_board, phy_en_char_align must be connected only when 8B10B encoding is used,
otherwise this signal does not exists in the JESD ip and will cause an error.
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
New improvements for the ADI DMAC IP:
1)The capability to manually overwrite the DMA_AXI_ADDR_WIDTH(from GUI or from tcl)
2)DMA_AXI_ADDR_WIDTH attribute is now visible in the Vivado GUI:
-"Auto mode": Automatically calculated by the core tcl files based on the existing attached address segments.
-"Manual mode": Specify the desired dma_width between 32-64 bits.
3)Added two new debug registers that return higher part of the current source/destination address.
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
laurent-19
Stanca Pop
Sergiu Arpadi
Paul Pop
Jem Geronimo
Iulia Moldovan
alin724
Istvan-Zsolt Szekely
AndrDragomir
LIacob106
Filip Gherman
AndreiGrozav
Ionut Podgoreanu
Bogdan Luncan
Travis F. Collins