Commit Graph

9 Commits (1b713d8265d00b6ff1167d9d804a125cbfcb24ac)

Author SHA1 Message Date
Laszlo Nagy bed5ce516c adcfifo/dacfifo: fix alignments 2019-01-23 14:45:45 +02:00
Laszlo Nagy a3766b464b adcfifo/dacfifo: Use proc to create infrastructure
Create the dacfifo/adcfifo infrastructure with procedures.
This will allow moving the parameters of the dac/adcfifo inside
the block design so it can be calculated based on other parameters.
2019-01-23 14:45:45 +02:00
Istvan Csomortani e3ea51ade3 avl_dacfifo: Refactor the fifo
+ Build both the read and write logic around an FSM
 + Consistent naming of registers and wires
 + Add support for burst lenghts higher than one, current burst lenght
is 64
 + Fix all the bugs, and make it work (first bring up with
adrv9371x/a10soc)
2017-10-31 14:30:06 +00:00
Istvan Csomortani 07f3295638 common/a10soc: Update configuration for emif plddr4 IP 2017-09-25 08:57:26 +01:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty b3ce821311 change pl ddr clock to 1G 2017-05-01 09:35:10 -04:00
Istvan Csomortani 6ed721ee66 adrv9371/a10soc: Integrate the avl_dacfifo into project 2017-04-21 13:27:35 +03:00
Rejeesh Kutty 3fa9a30f0e a10soc/plddr4- lower mem clk to meet timing 2017-03-06 14:12:25 -05:00
Rejeesh Kutty aad41039bd a10soc- plddr4 settings 2017-02-28 13:36:28 -05:00