6 Commits (1b19a1b78acecd4539cb692bf7928ffcc7774be6)

Author	SHA1	Message	Date
Lars-Peter Clausen	c7989925c5	fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock ... Otherwise we get timing errors for the reset signal that is generated in the 50MHz clock domain, but used in the VGA PLL clock domain. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2014-09-09 15:05:06 +02:00
Lars-Peter Clausen	50faf0c53a	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
Rejeesh Kutty	59759a8ab3	c5soc: working hdl version	2014-07-24 20:51:41 -04:00
Rejeesh Kutty	c0e31aa6c2	daq2: latest hardware	2014-07-21 09:06:57 -04:00
Rejeesh Kutty	a388ccab0a	fmcomms2/c5soc: initial checkin	2014-07-02 14:56:00 -04:00
Rejeesh Kutty	9a08189b93	c5soc: initial a5soc copy	2014-07-01 13:09:38 -04:00