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3 Commits (1aac44b0d97f0c72b408ada21a43fc546bc18119)

Author SHA1 Message Date
Istvan Csomortani e381d5170c util_tdd_sync: Update the synchronization interface 
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
 2016-02-12 14:27:37 +02:00
Istvan Csomortani bdf9754971 util_tdd_sync: Sync signals output reg is a false path source 2015-11-17 09:42:05 +02:00
Istvan Csomortani a290611c09 util_tdd_sync: Initial commit 
A synchronization signal generator for AD9361 running on TDD mode.
If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
 2015-11-11 10:46:11 +02:00