Commit Graph

1891 Commits (1a9497b5b6d63d06c12b4d76563bc904b594dc52)

Author SHA1 Message Date
Istvan Csomortani d13ff8df1e axi_dmac: In SDP mode REGCEB is connected to GND
In newer version of Vivado (e.g. 2017.4) the REGCEB pin of the block ram
macro is connected to ground. So the following false path became
redundant.
2018-04-11 15:09:54 +03:00
Istvan Csomortani fcbc977cd8 axi_ad7616: Add missing port to instantiation 2018-04-11 15:09:54 +03:00
Istvan Csomortani f605b428fc spi_engine:axi_spi_engine: Add missing port to instantiations 2018-04-11 15:09:54 +03:00
Istvan Csomortani 7d0b162eda axi_ad9963: Fix port dependency definition 2018-04-11 15:09:54 +03:00
Istvan Csomortani a7b98c397a ad_tdd_control: Fix the tdd_burst_counter implementation 2018-04-11 15:09:54 +03:00
Istvan Csomortani cd94f2f249 util_axis_upscale: Initial commit
This module upscale an n*sample_width data bus into a 16 or 32*n data
bus. The samples are right aligned and supports offset binary or two's
complement data format.
2018-04-11 15:09:54 +03:00
Istvan Csomortani 269ae40f66 spi_engine: Add support for 8 SDI lines 2018-04-11 15:09:54 +03:00
Istvan Csomortani e16f45c792 util_pulse_gen: Use equal-to for counter reset 2018-04-11 15:09:54 +03:00
Adrian Costina 017dcaed82 up_[adc|dac]_common: DRP_DISABLE should be boolean 2018-04-11 15:09:54 +03:00
Adrian Costina d3bfb33871 constraints: up_xfer_cntrl and up_xfer_status have its own constraints
The up_xfer_cntrl and up_xfer_status modules have its own constraints files
in library/xilinx/common. Each IP which has an instance of these
modules, have to use these constraints files.

The following IPs were modified:
  - axi_adc_decimate
  - axi_adc_trigger
  - axi_dac_interpolate
  - axi_logic_analyzer
2018-04-11 15:09:54 +03:00
Laszlo Nagy ae02773480 axi_dacfifo: Rewrote constraints to be more specific
Some of the wildcards matched too many paths and disabled the timing
checks on intraclock paths.
2018-04-11 15:09:54 +03:00
Adrian Costina b2d63bf9e0 axi_ad9434: Make adc_enable controllable from the channel register map 2018-04-11 15:09:54 +03:00
Adrian Costina 493fc1d48b axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
A couple of new parameters and new ports are missing in several
up_[adc|dac]_[common|channel] instance, and generates warnings. The rule of
thumb is to use full instantiations, defining all the existing parameter and
ports of the module.

Fix all the instantiation of up_[adc|dac]_[common|channel], by defining all its
parameters and ports.
2018-04-11 15:09:54 +03:00
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
2018-04-11 15:09:54 +03:00
Istvan Csomortani 3b34e8b594 up_clock_com: Fix the false path definitions for CDCs 2018-04-11 15:09:54 +03:00
AndreiGrozav c313c67585 axi_adcfifo_constr.xdc: Add missing backslash to command 2018-04-11 15:09:54 +03:00
Istvan Csomortani d81f605ae9 axi_ad9162: Fix code alignment, no functional changes 2018-04-11 15:09:54 +03:00
Istvan Csomortani 758c617c77 common/up_* : Make up_rstn synchronous to up_clk
The up_rstn is driven by s_axi_resetn, which is generated by a
Processor System Reset module. (connected to port peripheral_aresetn)
Therefor using this reset signal as an asynchronous reset is redundant,
and a bad design practice at the same time. Asynchronous reset should be
used if it's inevitable.
2018-04-11 15:09:54 +03:00
Adrian Costina 8234ba1029 scripts:adi_ip: Update web address format
Change format for web address so that IP GUI considers it valid
2018-04-11 15:09:54 +03:00
Istvan Csomortani 7c04e36656 scripts: Message severity changes on Vivado
Vivado sometimes generates semi-valid or invalid warnings and critical warnings.
In the past these messages were silenced, by changing its message severity.
These setups were scattered in multiple scripts. This commit is an attempt
to centralize it and make it more maintainable and easier to review it.
2018-04-11 15:09:54 +03:00
Istvan Csomortani 47e95fc4a9 scripts: Update tools for the next release
The next supported tool versions are:
  + Vivado 2017.4.1
  + Quartus 17.1
2018-04-11 15:09:54 +03:00
Istvan Csomortani 377848ef52 cftl: Delete unused projects and libraries 2018-04-11 15:09:54 +03:00
Istvan Csomortani bee392253b jesd204:tb: Fix the loopback_tb test bench
The jesd204_rx instantiation contained a port that did not exist. (phy_ready)
2018-03-28 15:19:18 +01:00
Adrian Costina 9baf910339 axi_logic_analyzer: Fix push-pull/open-drain selection 2018-03-07 10:19:51 +02:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
Lars-Peter Clausen e95f1b282e Remove unused Q_OR_I_N parameter from JESD204 ADC cores
The cores that handle the JESD204 ADC cores do not feature IQ correction
logic. The Q_OR_I_N parameter for the channel modules is unused, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-20 16:33:16 +01:00
Lars-Peter Clausen 0c2fad54d7 Remove unused IO_DELAY_GROUP parameter from JESD204 ADC cores
The cores that handle the JESD204 ADC converters do not feature any direct
IO and subsequently no IO-delay blocks either. Remove the unused
IO_DELAY_GROUP parameter.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-20 16:33:16 +01:00
AndreiGrozav 64c8fd7e5e axi_clkgen: add ultrascale series support 2018-02-13 17:33:38 +02:00
Matt Fornero 3e7399913f axi_dmac: Include TLAST in AXIS slave port
Bundle the TLAST signal in with the other AXIS slave signals to enable
easier connection between AXIS devices that use TLAST

Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2018-01-23 17:43:48 +01:00
Lars-Peter Clausen c6073954d9 axi_dmac: Add limited TLAST support for streaming AXI source interface
Add some limit TLAST support for the streaming AXI source interface. An
asserted TLAST signal marks the end of a packet and the following data beat
is the first beat for the next packet.

Currently the DMAC does not support for completing a transfer before all
requested bytes have been transferred. So the way this limited TLAST
support is implemented is by filling the remainder of the buffer with 0x00.

While the DMAC is busy filling the buffer with zeros back-pressure is
asserted on the external streaming AXI interface by keeping TREADY
de-asserted.

The end of a buffer is marked by a transfer that has the last bit set in
the FLAGS control register.

In the future we might add support for transfer completion before all
requested bytes have been transferred.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-01-23 17:43:48 +01:00
Lars-Peter Clausen da28ee3cce axi_ad9361: xilinx LVDS interface: Restore previous feedback clock polarity
Commit ff50963c7f ("axi_ad9361- altera/xilinx reconcile- may be broken-
do not use") inverted the polarity of the TX feedback clock.

This exposed some issues in the existing drivers which can cause the
interface tuning to fail randomly under certain conditions.

To keep backwards compatibility with existing drivers restore the previous
behavior.

A separate fix will be applied to the drivers that resolves the issue that
has been exposed by the polarity inversion. So that interface calibration
works reliably under all conditions.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-01-19 18:17:50 +01:00
AndreiGrozav 92321f0534
ad9434: Specified DEVICE_TYPE parameter options 2018-01-19 14:13:37 +02:00
AndreiGrozav 28830b4b66
axi_ad9434.v Add description for parameter 2018-01-18 15:52:11 +02:00
AndreiGrozav d44f7d1e4f axi_ad9434: Fix bad parameter definition
Assigning the value of a local parameter(localparam) to a parameter
will end up with a conflict(not highlighted by the tool). In this
case, the parameter type was defined as a string instead of an
integer. Furthermore, this scenario leads to an undesired choice
between primitive types.
2018-01-18 14:46:08 +02:00
Istvan Csomortani 3e3955ce91 avl_dacfifo: Fix avl_address generation
+ Define address limit at 2GByte
  + Address is WORD aligned, increment accordingly
2017-12-15 12:17:47 +00:00
Istvan Csomortani 60d2fb939d avl_dacfifo: Control the avl_burstcount inside the FSM 2017-12-15 08:56:57 +00:00
Istvan Csomortani b8e8410cbc avl_dacfifo: Fix the last address buffer control 2017-12-15 08:56:57 +00:00
Istvan Csomortani aaff5a8d6a avl_dacfifo: dma_last_beats is transfered to avalon clock domain, without conditioning
The dma_last_beats is used by the Avalon Memory Mapped interface
controller, to define the last burst length.
Its value get stable after the last valid data of the DMA interface, and staying
stable until the positive edge of the DMA's xfer_req.

No need to condition the transfer of this register to avalon clock
domain.
2017-12-15 08:55:01 +00:00
Istvan Csomortani 6bbf1ae83c avl_dacfifo: End of burst is not always end of a transaction
The XFER_END state defines the end of a transaction, when the entire
data set is written or read to/from the DDRx memory.
A transaction can contain multiple Avalon bursts. Make sure that the FSM
goes back into staging phase at the end of each burst; also define a
signals which indicate the end of each burst for control.
2017-12-09 09:56:33 +00:00
Luca Ceresoli ba24909a25 axi_streaming_dma_rx_fifo: fix period_count clock and TLAST
The period_count should be updated once per clock cycle. This is not
enforced with the current implementation, which probably leads to
period_count being decremented on both m_axis_aclk edges.

A problem observed due to this is that the m_axis_tlast output is not
asserted or is asserted for a too short time for the consumer to
detect it.

Fix by letting the decrement (and thus the m_axis_tlast toggling)
happen only on the rising edge of the m_axis_aclk clock.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
2017-12-05 13:04:46 +00:00
Istvan Csomortani 2b2c6b57f9 axi_dmac: Align the data_ready to data
The commit 6900c have added an additional register stage into the fifo read
data path, but the control signals (ready/valid/underflow) were not realigned
to the data. This can cause data lose or duplicated samples in some case.
Realign the control signals to the data.
2017-11-21 13:15:03 +00:00
Adrian Costina b54dab33e0 Make: Update makefiles 2017-11-20 14:27:39 +02:00
AndreiGrozav 74ad0d1e46 library: Update
Older Vivado versions where incorrectly inferring interfaces
-axi_ad9361
-axi_ad9963
-axi_adc_decimate
-axi_adc_trigger
-axi_clkgen
-axi_dac_interpolate
-axi_hdmi_tx
-axi_i2s_adi
-axi_logic_analyzer
-spi_engine
2017-11-15 17:08:45 +02:00
Lars-Peter Clausen 631f9253b2 axi_adxcvr: Correctly report the transceiver type in the register map
The util_adxcvr supports GTX2, GTH3 and GTH4. The transceiver is selected
using the XCVR_TYPE parameter.

The axi_adxcvr on the other hand only has a configuration parameter to
indicate whether a GTX or GTH transceiver is used (GTH_OR_GTX_N). Since
there are some minor differences between GTH3 and GTH4 that software needs
to know about rename the GTH_OR_GTX_N to XCVR_TYPE and match use the same
semantics as util_adxcvr.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
Istvan Csomortani 6900c9979b axi_dmac: Reset fifo_rd_data without delaying the valid data 2017-11-03 13:41:50 +00:00
Istvan Csomortani 960883c789 avl_dacfifo: Fix dac_xfer_req generation
The dac_xfer_req should indicate one single thing, that the FIFO is in
read phase. Should not be affected by any signals, which indicates data
validity on any interface. (e.g. dac_valid)
This signal is not used by the device core, its main purpose is to
indicate the state of the interface for a posible intermediat processing
module.
2017-11-03 09:32:10 +00:00
Istvan Csomortani 572cd10c35 avl_dacfifo: Fix reset architecture in avl_dacfifo_rd
Make sure that all address registers are reset during the initialization
phase of the FIFO.
2017-11-03 09:29:43 +00:00
Istvan Csomortani 17c749962c avl_dacfifo: Fix the loopback of avl_xfer_req
When the read FSM is not in a burst, the incomming avl_xfer_req can be
looped back to the write module.
2017-11-02 12:02:54 +00:00
Istvan Csomortani 610a237730 avl_dacfifo: Fix write enable generation
Data is written into the CDC FIFO if both dma_ready and dma_valid are
asserted. This two signals is enough to validate the data coming from
the DMA.
2017-11-01 12:22:18 +00:00
Istvan Csomortani 6895915076 avl_dacfifo: Fix reset of write address register
Fix the reset of the dma_mem_waddr (write address register of the CDC
FIFO on DMA's clock domain). This solves the occasional invalid read backs after
multiple re-initialization of the PL_DDR_FIFO.
2017-11-01 12:21:56 +00:00