ab8627e669
fmcomms1: Changed ILA data capture and sys constraints
...
The ILA can not work at 250MHz on ZED/ZC702. Because of this, the data
path was modified from 28bits@250MHz to 56bits@125MHz, by using a FIFO.
The ZED/ZC702 max BUFG frequency is 464MHz, which corresponds to a 2.16
period so the constraints were modified accordingly.
2014-03-17 15:50:01 +02:00
522a222d3a
axi_dmac: Fix default value for DMA type
...
Vivado doesn't handle the case where we use symbolic constants for the default
value properly, so update this to use plain integers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-17 13:20:49 +01:00
ad491e92ab
changed pcore version and made it local (top shouldn't override)
2014-03-14 12:02:16 -04:00
ee56db8d50
FMCOMMS2: Modified FCLK2 to 125 MHz, and xdc file
...
tcl: FCLK2 was modified from 100 MHz to 125 MHz.
xdc: rx_clk period constraint was redefined from 8ns (125 MHz) to 4ns (250 MHz)
2014-03-14 16:27:56 +02:00
8394532c12
Update README.md
2014-03-13 14:03:15 -04:00
21d4c25586
Update README.md
2014-03-13 14:02:46 -04:00
f02ba999ae
axi_dmac: Add support for DMA bus widths other than 64 bit
...
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-13 13:20:10 +01:00
7a6ce70e19
Fix default repository path for adi_project.tcl
...
Projects can be build by running 'source system_project.tcl' in
Vivado Tcl console.
2014-03-13 10:28:16 +02:00
fd14607da5
mult instances: consistent naming style
2014-03-12 15:42:47 -04:00
64a89ff66b
Merge branch 'master' of github.com:analogdevicesinc/hdl
2014-03-12 15:36:00 -04:00
7fc5b8ecd9
common: use dsp slice for multiply modules
2014-03-12 15:35:21 -04:00
ba484999b3
Fix default value of $ad_hdl_dir and $ad_phdl_dir
2014-03-12 18:18:47 +02:00
cda3cb3280
removed misc stuff
2014-03-12 11:02:53 -04:00
a6c3cb29c6
Modified SPI and ILA in fmcomms2_bd.tcl
2014-03-12 16:52:22 +02:00
92aaf0bd51
FMCOMMS1: Updated projects and axi_ad9643 core
...
ZC702: Removed invalid address segments. Changed the constraints
for adc_clk to minimum possible value in order to meet timing.
ZED: Change the constraints for adc_clk to minimum possible value, in
order to meet timing
AXI_AD9643: Corrected the number of bits in the adc_mon_data bus
2014-03-12 16:23:41 +02:00
66c6b2b182
fmcomms2: added
2014-03-11 20:04:26 -04:00
580808e146
axi_ad9361: added
2014-03-11 20:01:55 -04:00
380584c23b
Update LICENSE
2014-03-11 15:06:52 -04:00
a9df18b4ec
Update LICENSE
2014-03-11 15:05:18 -04:00
f8ab734918
projects/fmcomms1: added
2014-03-11 12:16:25 -04:00
a76d6c4686
library/axi_ad9122,axi_ad9643: added
2014-03-11 12:13:25 -04:00
e1f23e7d49
Merge branch 'master' of github.com:analogdevicesinc/hdl
2014-03-11 09:58:34 -04:00
f3ae57a53e
global clock and reset names
2014-03-11 09:57:59 -04:00
77ed085641
Update README.md
2014-03-10 16:41:22 -04:00
0817973cc0
library: removed xilinx dc filter and dds
2014-03-10 14:52:48 -04:00
f9dfd944c9
library/util_fifo: updates for read side
2014-03-10 14:48:14 -04:00
75963ab376
Initial check in of VC707 base project
...
- All source files for the VC707 base project
- Update the common base system to the new naming convention
2014-03-10 17:26:17 +02:00
a6d747411e
util_wfifo: ip cleanup
2014-03-10 11:21:20 -04:00
bb0431d3e8
library: dds and dcfilter changes, added fifo wrappers
2014-03-10 11:11:50 -04:00
d6256e9e29
library: dds and dcfilter changes, added fifo wrappers
2014-03-10 11:11:16 -04:00
8326022adc
axi_dmac: address_generator: Fix disable race condition
...
If the address generator is disabled the very same cycle as it tries to put a
new address on the bus, it will keep sending this address forever and the core
will lock up
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-07 18:40:49 +01:00
6da9c65a08
axi_dmac: Add support for zero latency transfer switching
...
Right now there is always a period of one clock cycle where we can not transfer
any data when switching between two transfers. This patch modifies the data
mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-07 18:39:20 +01:00
f07b74ecdd
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-03-07 14:03:12 +02:00
793bf2f350
Change the adi_project_run process to prevent "const_type UCF" issue
...
- Set the constraint type to XDC before run the synthesis
2014-03-07 11:06:11 +02:00
23a62a92b2
up_adc_common: dma bus width is 0x8 (constant)
2014-03-06 19:22:19 -05:00
32c2abf4e6
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-03-06 18:16:53 +02:00
831c19ea84
Added axi_dmac, axi_fifo and misc files in library
2014-03-06 18:16:02 +02:00
5c3b65d01b
adv7511: kc705/ac701 updates
2014-03-06 09:36:50 -05:00
3becfd5d51
added gitignore
2014-03-05 10:47:16 -05:00
b0a1fab743
adv7511/kc705: added
2014-03-05 10:43:16 -05:00
360f10395a
initial checkin
2014-03-03 13:42:25 -05:00
82115b138e
adv7511/ac701: initial checkin
2014-03-03 13:40:24 -05:00
c89477be5a
projects/adv7511: zynq boards
2014-03-03 10:16:49 -05:00
350ec5e633
changed path settings
2014-03-03 10:06:36 -05:00
3c0ea759a0
changed path settings
2014-03-03 10:06:02 -05:00
ddac1a8834
added common board files
2014-02-28 21:17:01 -05:00
63bd2b870a
pointers to directories
2014-02-28 16:58:30 -05:00
ff5021b1a8
pointers to directories
2014-02-28 16:57:19 -05:00
f7c9368abc
initial checkin
2014-02-28 14:26:22 -05:00
64b7269288
Initial commit
2014-02-20 12:49:14 -08:00
Adrian Costina
Lars-Peter Clausen
Rejeesh Kutty
ATofan
Istvan Csomortani