Commit Graph

10 Commits (14b4c4cf5ff16a1878683c53fc9074d0473325ae)

Author SHA1 Message Date
AndreiGrozav 9d6c93a5d8 Fix warnings 2016-11-14 15:17:15 +02:00
Istvan Csomortani 18e28b01fd axi_ad7616: Add burst counter to the parallel interface
With this counter the parallel logic supports the burst sequencer.
2016-06-29 14:17:28 +03:00
István Csomortáni 583bafd17a axi_ad7616: Add a new register for IF_TYPE
Add an additional new read only register at 0x03 address for the interface type. This way the software can verify the actual interface mode.
2016-05-04 16:14:29 +03:00
Istvan Csomortani 33199263e1 axi_ad7616: Delete burst_length register
This was an unnecessary feature of the hdl core.
2016-04-29 16:28:48 +03:00
Istvan Csomortani d5d7c12f0e axi_ad7616: Fix the register map 2016-04-25 11:36:39 +03:00
Istvan Csomortani fbb0d368bf axi_ad7616: Add support for parallel interface 2016-01-28 12:37:22 +02:00
Istvan Csomortani cd43ebd8bc axi_ad7616: The OP_MODE parameter is no longer required 2016-01-26 11:05:33 +02:00
Istvan Csomortani 2a17ce275c axi_ad7616: Control inputs are controlled through GPIO
The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
Istvan Csomortani 8ae9de8fba axi_ad7616: Update core
+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
2015-12-14 16:00:56 +02:00
Istvan Csomortani d6eae81bc1 axi_ad7616: Add the control module to the core, finish up SPI integration 2015-11-13 18:14:21 +02:00