9cdec38532
gt- report device type
2015-02-17 11:43:57 -05:00
2442b6e929
gt- report device type
2015-02-17 11:43:50 -05:00
fccadcec31
jesd_gt: lpm/dfe programmable
2015-02-13 11:33:25 -05:00
de043ce130
gt_channel: lpm/dfe programmable
2015-02-13 11:33:04 -05:00
870ebdb562
up_gt: support lpm mode
2015-02-12 16:21:11 -05:00
1e7c9a3924
gt_es: support lpm mode - 2/2
2015-02-12 16:20:43 -05:00
0a8e6f62ef
gt_es: support lpm mode - 1/2
2015-02-12 15:15:18 -05:00
9e2e2ef44e
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:16 -05:00
e9231c8f36
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:14 -05:00
518d842af9
upack: initial commit
2015-02-06 15:15:33 -05:00
d02c21b426
util_pmod_adc: General update
...
Redesign the state machine, rename constant and variable names, add notes and description.
2015-02-04 14:49:16 +02:00
96899313d8
axi_dmac: Fix constraint
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Change the constraint file extension to .xdc, no more need for the .tcl workaround.
2015-01-23 18:51:25 +02:00
b10ba49425
axi_dmac: Fix constraint related issue
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Tcl command "if" is not supported by Vivado XDC, therefore the tool throw some critical warnings, and does not
apply the constraints, which can cause timing violations at case of some carriers.
The following solution is much more compact and is supported by the XDC, and more importantly prevents
unwanted critical errors and timing violations.
2015-01-23 18:44:17 +02:00
d5bd485624
axi_dmac: Fix eot issue under 2014.4
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Vivado 2014.4 is too greedy, when it needs to optimize. See more about the issue here: https://ez.analog.com/thread/48214
The response_dest_resp is unused, so not save to concatenate with a valid signal like the eot.
2015-01-23 18:39:33 +02:00
659e0cca4e
cftl_cip: Initial check in.
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Project cftl_cip supports the following Circuits from the Lab pmods:
+ EVAL-CN0350-PMDZ
+ EVAL-CN0335-PMDZ
+ EVAL-CN0336-PMDZ
+ EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
5a1819ed6e
fifo2s: qualify last with valid
2015-01-15 15:42:10 -05:00
debbe31713
Merge remote-tracking branch 'origin/master' into dev
2015-01-09 11:12:56 -05:00
63633a0fa5
ad9739a: constraints
2015-01-08 10:25:45 -05:00
ed73a9d1cf
ad9739a: updated to ad9739a
2015-01-08 10:25:15 -05:00
14df46c193
library: Initial commit of axi_hdmi_rx ip core
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Status unknown, NOT tested.
2015-01-08 16:58:56 +02:00
9f485f2f4e
common: Add register map module for HDMI receiver.
2015-01-08 12:24:47 +02:00
161e6cc70d
common: Add color space sampling and color space conversion modules
...
This two module are used by the HDMI receiver.
2015-01-08 12:24:46 +02:00
ad4b4f64d0
ad9739a: ad9122 copy
2015-01-07 15:36:02 -05:00
3a4d765a2b
up_clkgen: reading typo
2015-01-07 14:02:39 -05:00
b65bcab8d6
up_clkgen: reading typo
2015-01-07 13:58:43 -05:00
5f93c859b5
util_rfifo: renamed ports to make vivado happy
2015-01-06 16:16:42 -05:00
8056574bae
util_wfifo: renamed ports to make vivado happy
2015-01-06 16:16:25 -05:00
0291bb3bf7
util_rfifo: port name fixes & doc.
2015-01-06 16:15:51 -05:00
36b041ccc0
util_wfifo: port name fixes & doc.
2015-01-06 16:15:42 -05:00
ee0912eb6a
ad9361: make 2t2r external for mw
2015-01-05 10:54:23 -05:00
c3529f112f
up_gt: move status to up clock
2014-12-19 13:00:27 +02:00
f4774d6f98
fifo2s: false path typo on source signals
2014-12-19 13:00:13 +02:00
1d6ea64d04
up_gt: move status to up clock
2014-12-16 08:48:13 -05:00
16f64a75d6
fifo2s: false path typo on source signals
2014-12-15 13:00:13 -05:00
04c10abc2f
gth/gtx: share same cpll/qpll cpu settings
2014-12-11 11:18:48 -05:00
c4152627f0
plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width
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The adc_wcnt_int must be synchronized to adc_wr. The adc_dwr signal pulse width was to long,
it needs to be just one adc_clk cycle.
2014-12-09 13:59:19 +02:00
19732d89fb
plddr3: Fix the adc_dwr pulse width
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The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
2014-12-09 13:51:00 +02:00
6aad2fbbb2
axi_hdmi_tx: Fixed typo in altera related core
2014-12-09 10:19:03 +02:00
6f8c259961
axi_hdmi_tx: Fixed typo in altera related core
2014-12-09 09:56:14 +02:00
a70d27c094
axi_mc_speed: updated core to latest axi interface implementation
2014-12-05 11:53:11 +02:00
26f58914e2
axi_mc_current_monitor: updated core to latest axi interface implementation
2014-12-05 11:53:06 +02:00
7e8e1e4fd0
axi_mc_controller: updated core to latest axi interface implementation
2014-12-05 11:52:59 +02:00
ea1a50c985
axi_mc_speed: updated core to latest axi interface implementation
2014-12-05 11:46:20 +02:00
0d2888a5a6
axi_mc_current_monitor: updated core to latest axi interface implementation
2014-12-05 11:45:37 +02:00
21591dc485
axi_mc_controller: updated core to latest axi interface implementation
2014-12-05 11:43:59 +02:00
6197563506
up_axi: Fix up_raddr/up_waddr port width
...
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
8cc9adfc49
up_axi: Fix up_raddr/up_waddr port width
...
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:22:28 +01:00
afddc45ba4
library/ccat: initial commit
2014-11-25 12:59:51 -05:00
196e8b119c
library/bsplit: initial commit
2014-11-25 12:59:50 -05:00
403f8c0631
util_cpack: ipi doesn't like local params
2014-11-21 15:32:13 -05:00
3b500bafcc
util_cpack: add port controls on ipi
2014-11-21 15:32:12 -05:00
5ca2944b70
library/util_cpack: initial checkin
2014-11-21 15:32:10 -05:00
42874bfe81
prcfg_library: Major update
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Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
2014-11-18 10:05:52 +02:00
a4724f8396
es: added kcu105 gth
2014-11-17 09:55:12 -05:00
b1c91fac92
es: added kcu105 gth
2014-11-17 09:55:10 -05:00
fd305f2eff
es: added kcu105 gth
2014-11-17 09:55:09 -05:00
6dd1226696
axi_ad9643: Fixed constraint file
2014-11-17 12:12:09 +02:00
8831d9dbd7
axi_ad9122: fixed constraint file
2014-11-17 12:11:20 +02:00
2744d0cb37
util_wfifo: Update to implement flip flops
2014-11-17 12:10:21 +02:00
41ffc66c26
fifo2s: removed m interface
2014-11-13 15:00:03 -05:00
8761db438e
axi_fifo2f: common interface with fifo2s
2014-11-12 15:15:32 -05:00
925e966eb6
axi_fifo2s: fifo full replaced with ready
2014-11-12 14:43:47 -05:00
5fc4f1b000
axi_fifo2s: buswidth fix
2014-11-12 14:43:46 -05:00
d204a7c2b7
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:44 -05:00
e7cec7171e
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:43 -05:00
4381f20a6a
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:42 -05:00
9f2dbad539
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:41 -05:00
e683b5868e
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:40 -05:00
81b4cd532d
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:38 -05:00
888ab888d2
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:37 -05:00
f8e7796592
axi_jesd_gt: Fix lane number parameters
2014-11-12 17:43:32 +02:00
bf62665c56
prcfg_qpsk: Add Simulink model
...
Matlab version used: R2014a, HDL Coder 3.3
2014-11-12 15:44:38 +02:00
64ec633438
gt: asymmetric no of lanes
2014-11-11 08:54:24 -05:00
cb15567a56
ad6676: added
2014-11-10 13:36:07 -05:00
c6df568a00
Revert "ad_interrupts: Initial check in."
...
This reverts commit b254380338
2014-11-06 12:16:52 +02:00
b11d80ed98
ad_rst: changed to dual stage
2014-11-05 16:48:02 -05:00
74ec396b27
ad_rst: ultrascale -dual stage
2014-11-05 16:47:41 -05:00
d69ccebbde
ad9234: full 16bit samples
2014-11-05 11:59:08 -05:00
403fe1b373
wfifo: read only if ready is asserted
2014-10-31 13:05:17 -04:00
38652b1c3e
axi_ad9643: Added constraint file
2014-10-31 17:57:47 +02:00
3e9ce71d21
axi_ad9122: Added constraint file
2014-10-31 17:56:56 +02:00
d596d71285
prcfg_qpsk: Swap the I/Q pair nets between the filter and the demodulator.
...
This fix the wrong symbol mapping issue.
2014-10-31 12:14:52 +02:00
eb520b1f75
prcfg_qpsk: Major update
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Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.
2014-10-31 12:10:59 +02:00
ea194755e1
prcfg: Upgrade the QPSK logic
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Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
2014-10-31 11:59:29 +02:00
9818bcb601
axi_fifo2f: internal memory low overhead
2014-10-30 11:12:10 -04:00
17cb1d9585
common/mem: asymmetric version
2014-10-30 11:12:09 -04:00
6470ea91ad
axi_fifo2f: fake version
2014-10-30 11:12:08 -04:00
f9628262aa
axi_dmac: Add xfer_req signal to the streamin AXI source interface
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
fbce64411e
axi_ad9671: added synchronization interface to altera core
2014-10-29 18:20:26 +02:00
36c7034bd6
ad7175: Fix dma issues
2014-10-28 16:00:06 +02:00
9c8fe5f09c
ad7175: Removed unused files
2014-10-28 14:30:41 +02:00
9e1d1c1b49
ad7175: Updated the AD7175 IP and project
2014-10-28 14:28:38 +02:00
b254380338
ad_interrupts: Initial check in.
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Initial check in of the interrupt concatenation block.
2014-10-27 19:34:34 +02:00
e086f5eb9f
axi_ad9361: Updated core with the new up_adc_common register set
2014-10-27 19:26:40 +02:00
7e52cf9568
up_axi: timeout generating multiple/repeated acks
2014-10-23 13:51:33 -04:00
3dbfa8cda6
ad9434_fmc: Fix PN monitor and device interrupt
2014-10-23 11:29:14 +03:00
b9ca616150
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-23 06:11:52 +03:00
da8454ae4c
axi_ad7175: Added the AD7175 IP
2014-10-23 06:11:41 +03:00
6f723ef9e5
axi_jesd_gt: lane mux on char qualifiers
2014-10-22 15:29:25 -04:00
fe92b8b210
axi_ad9671: Updated synchronization mechanism to have a software defined starting code
2014-10-22 13:10:28 +03:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen
acozma