Commit Graph

3836 Commits (139876d28a25e054fe8305b513f1ad1e8d992264)

Author SHA1 Message Date
Lars-Peter Clausen 139876d28a up_clock_mon: Remove extra hold register
Currently the clock monitor features a hold register in the monitored clock
domain. This old register is used to store a instantaneous copy of the
counter register. The value in the old register is then transferred to the
monitoring domain. Since the counter is continuously counting it is not
possible to directly transfer it since that might result in inconsistent
data.

Instead stop the counter and hold the registers stable for a duration that
is long enough for the monitoring domain to correctly capture the value.
Once the value has been transferred the counter is reset and restarted for
the next iteration.

This allows to eliminate the hold register, which slightly reduces
utilization.

The externally visible behaviour is identical before and after the patch.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 696305360c interfaces: Add dependencies to rule
Make sure that the XML files are re-build when any of the scripts that are
used to generated it are modified.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen a44420fa8f interfaces: Simplify Makefile
All the rules to generate the XML files are the same. Reduce the number of
rules by useing wildcard matching for the rule target.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Rejeesh Kutty 3db1050e91 pzsdr2/ccfmc: enable eth1 mdio 2017-05-22 13:38:36 -04:00
Rejeesh Kutty f09b902609 usdrx1- spi/mlo fixes 2017-05-22 13:22:44 -04:00
Adrian Costina 12930c8470 motcon2_fmc: Explicitly assign ETH0 MDIO to EMIO 2017-05-22 18:53:00 +03:00
Rejeesh Kutty 0930c486d2 axi_hdmi_rx- move data to an iob 2017-05-19 16:25:54 -04:00
Rejeesh Kutty 0eaa98370e fmcadc2/vc707- spi clock reg can't be on iob 2017-05-19 15:22:33 -04:00
Rejeesh Kutty eb7171e212 daq3/kcu105- reorder refclk constraints 2017-05-19 11:41:45 -04:00
Rejeesh Kutty 36037a76f8 kcu105- vivado now depends on order of constraints? 2017-05-19 11:21:36 -04:00
Rejeesh Kutty 0b3b1e6c76 kcu105- remove ethernet delay ctrl false path 2017-05-19 11:21:36 -04:00
Lars-Peter Clausen 858065d49b library: Sort Makefile
Sort the entries in the library Makefile alphabetical. Keeping it ordered
makes it easier to track changes compared to randomly reshuffling it
every time a new entry is added.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-19 15:33:26 +02:00
Lars-Peter Clausen e033d6c48e m2k: Refresh Makefile
The util_cpack core is currently not used by the M2K project. Refresh the
Makefiles to reflect this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-19 15:33:26 +02:00
Rejeesh Kutty 393577c911 util_adxcvr- 2016.4 gthe4 updates 2017-05-18 14:49:18 -04:00
Rejeesh Kutty f3959cb5b9 zcu102- 2016.4 updates 2017-05-18 14:17:20 -04:00
Rejeesh Kutty 4f0accbbfa adrv9371x fix dacfifo name 2017-05-18 12:54:14 -04:00
Rejeesh Kutty d507cd0c9a quartus optimization for frequency 2017-05-18 11:34:29 -04:00
Rejeesh Kutty 80a3f45b9f alt_mul- qsys replacement 2017-05-18 10:38:48 -04:00
Rejeesh Kutty ff7dc41066 alt-jesd- constraints update 2017-05-18 09:55:24 -04:00
Rejeesh Kutty d10faabc3f a10soc- 16.1- hsp sdram reset 2017-05-17 16:30:37 -04:00
Rejeesh Kutty f8f7bdd6a6 a10soc- fix version check 2017-05-17 16:26:28 -04:00
Rejeesh Kutty 598bd7e226 resolving conflicts 2017-05-17 16:18:53 -04:00
Rejeesh Kutty 6649b23bc8 alt-mem-asym - replace mega function cores 2017-05-17 16:13:26 -04:00
Rejeesh Kutty 828c2406cb adi-ip-alt allow changing device family 2017-05-17 16:13:26 -04:00
Rejeesh Kutty bea72232a3 alt_mem_asym- qsys component 2017-05-17 16:13:26 -04:00
Istvan Csomortani fe140a054f license: Fix VHDL license header 2017-05-17 18:28:06 +03:00
AndreiGrozav 70e3dd00ff scripts: Update required tool versions 2017-05-17 16:45:20 +03:00
Lars-Peter Clausen bf44f357fe Fix VHDL files license header, second try
While VHDL uses -- for comments uris still use //.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 15:25:08 +02:00
Lars-Peter Clausen 5ee9480142 Fix VHDL files license header
VHDL uses '--' for comments rather than '//'.

Also remove left over old license headers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 15:21:06 +02:00
AndreiGrozav 18bc5465df axi_usb_fx3: Add missing ports 2017-05-17 14:48:28 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
AndreiGrozav 857ad45d57 util_fir_int: Force 1/8 filter input data rate 2017-05-16 19:35:24 +03:00
AndreiGrozav 3f5d930cde axi_adc_decimate/cic_decim: Fix clk_enable warning
- fix clk_enable zero replication warning
2017-05-16 19:35:24 +03:00
AndreiGrozav fd7db4fcf3 util_tdd_sync: add missing ports 2017-05-16 19:35:24 +03:00
AndreiGrozav cf3737122b Remove duplicare wire declaration
-Introduced by updating to verilog-2001
2017-05-16 19:35:24 +03:00
AndreiGrozav 41e25e7c96 Add missing ad_serdes_out interface ports 2017-05-16 19:35:24 +03:00
Rejeesh Kutty c4b4bdc415 daq2/a10gx- constraints remove 16.0 2017-05-16 10:09:42 -04:00
Adrian Costina 0c5dabe358 axi_ad9963: Update constraints as adc_common and dac_common paths have been renamed 2017-05-15 18:59:09 +03:00
Adrian Costina ce4f9bf906 up_dac_common: rename internal signals 2017-05-15 18:58:26 +03:00
Rejeesh Kutty cfcb269d38 a10gx- change ddr to 1G 2017-05-15 09:32:36 -04:00
Rejeesh Kutty 63b701ccab altera- add version check 2017-05-12 15:13:29 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Rejeesh Kutty ecfa15bfce version check- change to critical warning 2017-05-12 09:51:48 -04:00
AndreiGrozav e4ae391237 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
AndreiGrozav 0e1e507541 axi dac cores: Add missing ports to up_dac_common instance 2017-05-12 13:37:34 +03:00
Rejeesh Kutty d93a6d062e fmcadc5-sync: added a convenience timer 2017-05-11 12:39:39 -04:00
Istvan Csomortani 8e7b577c94 axi_ad5766: Add missing ports to up_dac_common instance 2017-05-11 17:25:31 +03:00
Istvan Csomortani 6e5d965211 axi_ad5766: sdo_mem size is 3 2017-05-11 17:25:31 +03:00
Istvan Csomortani 7968ca64a6 axi_ad5766: Delete redundant parameters 2017-05-11 17:25:31 +03:00