06b28d2e24
ad9671: compile fixes
2014-04-11 14:28:22 -04:00
e92e6b2fd5
ad9671_fmc: changed for ad9671-fmc
2014-04-11 14:28:21 -04:00
72e318a247
ad9671_fmc: initial checkin
2014-04-11 14:28:20 -04:00
570ec26798
FMCOMMS2: Added sync option
2014-04-11 18:14:48 +03:00
99ef34936f
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-11 18:14:08 +03:00
c73390b6c9
axi_ad9361: Intermediary check in for altera porting
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This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
d0f04fd788
fmcomms1: Commit AC701 and VC707 projects
2014-04-11 17:35:25 +03:00
c718169f27
adi_board.tcl : Fix the address assignment command
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A lot of cores have more than one address segments, therefor need
to filter out the segment of the axi lite interface
2014-04-11 16:14:56 +03:00
cf5b9b51fd
adi_board.tcl : Fix spi ports and hp clocks
2014-04-11 15:31:12 +03:00
af07f8874f
wfifo/rfifo: asynchronous interface
2014-04-10 14:01:40 -04:00
37e2059fd0
adi_board.tcl : General update
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- Split the adi_dma_interconnect to two procedure:
adi_dma_interconnect and adi_hp_assign
- Fix the adi_spi_core
- Fix the adi_interconnect_lite
2014-04-10 18:29:14 +03:00
96541f0a7f
usdrx1: zc706 updated for usdrx1
2014-04-10 11:05:13 -04:00
6f36f74eea
usdrx1: common board files
2014-04-10 11:05:11 -04:00
ac1c145a61
usdrx1: initial checkin
2014-04-10 11:05:10 -04:00
dc7b3e085c
axi_dmac: Fix issues with non 64-bit AXI masters
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Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:54:22 +02:00
36ef882da0
axi_dmac: data_mover: Improve timing
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We do not know which 'last' condition to use before hand, but we can pre-compute
the result for both conditions and then use them. This removes the comparison
from the already pretty long combinatorial path.
Also simplify a few expressions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:06:44 +02:00
090d3aee04
axi_dmac: Change C_DMA_LENGTH_WIDTH default to 24
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
cb630e36a9
axi_dmac: src_fifo_inf: Simplify data path
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Improves timing a bit
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
f9ca4fb8be
axi_fifo: Slightly improve timing
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It is OK to overwrite invalid data with other invalid data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
4c9647f289
axi_dmac: axi_register_slice: Provide default values for registers
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
fa5ba6c09d
axi_dmac: Make cyclic mode runtime configurable
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
7ca43f4920
axi_dmac: address_generator: Make 'len' registered
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Slightly improves the timing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
66e6c1cc21
axi_dmac: axi_register_slice: Remove reset "latch" from datapath
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Move the datapath updates out of the else branch of the reset condition.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
799d2384d8
up_xfer_cntrl: Remove extra semicolon
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
9d19145713
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-10 10:50:53 +03:00
5aac9d7288
FMCOMMS2 added sync option
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Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
fbfd658f0d
zc706: added pl ddr3 mig
2014-04-09 15:58:12 -04:00
e73952a694
ad9467 : initial checkin
2014-04-09 17:34:40 +03:00
8bebc5e3d4
ad9671: initial checkin
2014-04-07 13:01:10 -04:00
5b0e37b97a
adi_project.tcl : Modify implementation strategy
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- Change implementation strategy to Performance Explore.
At some projects, this could prevent timing issues, it not
increase the overall implementation time in a dramatic way.
2014-04-07 15:02:38 +03:00
4116247fc0
Update README.md
2014-04-04 16:30:28 -04:00
33979fc533
fixes to improve timing - fifo for clock domain transfers
2014-04-04 13:49:53 -04:00
6a19b34a00
a5gt: added tightly coupled memory
2014-04-03 20:50:17 -04:00
04ab34c8ed
a5gt: ethernet assignments
2014-04-03 20:50:16 -04:00
12e5cc91bd
make signaltap/timing part of the flow
2014-04-03 20:50:15 -04:00
d0a8b4a63c
kc705,common: Mem_interconnect maximize performance
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For FMCOMMS1, when both the ADC and DAC DMAs are active, the system was
unstable. With this fix, it the system seems to be stable.
2014-04-03 15:59:33 +03:00
f8f2684b7e
up_gt: eyescan delay bug fix
2014-04-02 16:45:41 -04:00
e85153b5dd
altera hal version
2014-04-01 21:12:11 -04:00
80e5051894
axi_jesd_gt: initial checkin
2014-04-01 15:14:28 -04:00
2472d61daf
ad_gt_es: status asserted early for latency
2014-04-01 15:06:51 -04:00
04df908fbf
altera-fmcjesdadc1 initial checkin
2014-04-01 12:01:57 -04:00
0d678b89ed
altera a5gt fmcjesdadc1 setup
2014-04-01 11:46:37 -04:00
724bd70a06
altera additions and replacements
2014-04-01 11:18:10 -04:00
8deb36ce08
adi_board.tcl: All procedures works on Zynq/Microblaze
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General patch for the integration procedures. Tested on kc705 and
zed.
2014-04-01 16:19:24 +03:00
9676146725
FMCOMMS2 AC701 Project
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Not tested - must program Vadj on board
2014-04-01 15:35:44 +03:00
e597467447
FMCOMMS2 VC707 Project
2014-04-01 15:34:29 +03:00
814b0d72d6
Modified Reset signals for FMCOMMS2 base design
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Made all resets the same (sys_100m_resetn)
2014-04-01 15:32:48 +03:00
fbafaa8507
MicroBlaze base system: Fix a few net names
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Every interconnect interface net name follows the convention:
<interconnect name>_<interface name>
No changes in logic or any connection!
2014-04-01 10:40:35 +03:00
f0b8b8f6c0
FMCOMMS1: KC705 updated system_top and constraints
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Needed to be compatible with the latest common file
2014-03-31 17:49:10 +03:00
14b82c03dd
FMCOMMS1: Several modifications in the base design
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Corrected the ADC/DAC interrupt location for microblaze systems
Removed the ILA clock generation from sys_audio_clkgen and created a
separate clock generator
All system is reset from the same source
2014-03-31 17:44:57 +03:00
Rejeesh Kutty
ATofan
U-ANALOG\ACostina
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen
Istvan Csomortani