Commit Graph

5636 Commits (11822e2824030e49549bab715b9db3c4144447f7)

Author SHA1 Message Date
Lars-Peter Clausen b58a5c37eb m2k: Reduce AXI interconnect utilization
Use the new axi_rd_wr_combiner module to ... the read and write DMA
interfaces into a single interface. This allows the AXI interconnect
completely optimize itself away and reduce the overall resource utilization
of the project.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 71469490c6 Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface
The read and write interfaces of a AXI bus are independent other than that
they use the same clock. Yet when connecting a single read-only and a
single write-only interface to a Xilinx AXI interconnect it instantiates
arbitration logic between the two interfaces. This is dead logic and
unnecessarily utilizes the FPGAs resources.

Introduce a new helper module that takes a read-only and a write-only AXI
interface and combines them into a single read-write interface. The only
restriction here is that all three interfaces need to use the same clock.

This module is useful for systems which feature a read DMA and a write DMA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 3e0b337eae axi_ad9963: Remove extra pipeline stages on register read path
The register read logic is not that complicated that it needs two extra
pipeline stages. It can easily be condensed into a single combinatorial and
still meet timing with large margins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 64dfa0432d axi_ad9963: Disable unused features of the register map
Disable registers in the register map which are not needed for this core.
This reduces the utilization of the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 957730c421 up_dac_common: Allow to disable GPIO registers
Not all peripherals use the GPIO register settings, but the registers still
take up a fair amount of space in the register map. Add options to allow to
disable them when not needed. This helps to reduce the utilization for
peripherals where these features are not needed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 0ae0da488b up_adc_common: Allow to disable GPIO and START_CODE registers
Not all peripherals use the GPIO and START_CODE register settings, but the
registers still take up a fair amount of space in the register map. Add
options to allow to disable them when not needed. This helps to reduce the
utilization for peripherals where these features are not needed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:38 +02:00
Adrian Costina 71394ee465 kcu105: ip automatic version update 2017-04-18 11:59:54 +03:00
AndreiGrozav 01165c926c ad6676evb: Set default xcvr parameters to common design 2017-04-18 11:26:51 +03:00
Adrian Costina 942d69a30c Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
Adrian Costina 8e0c87e089 pluto: cleaned up some warnings 2017-04-18 10:34:13 +03:00
Adrian Costina f3c0be0868 motcon2_fmc: cleaned up some warnings 2017-04-18 10:33:13 +03:00
Adrian Costina 6e14cdb5f4 cftl_std: cleaned up some warnings 2017-04-18 10:32:28 +03:00
Adrian Costina d585d65692 cftl_cip: cleaned up some warnings 2017-04-18 10:29:20 +03:00
Adrian Costina 20672a3a8b mitx045: ip automatic version update 2017-04-14 17:46:25 +03:00
Adrian Costina 954037a716 microzed: ip automatic version update 2017-04-14 17:24:24 +03:00
Adrian Costina ebc04bcd9c usdrx1: ip automatic version update 2017-04-14 17:16:35 +03:00
Adrian Costina 24b797f1a6 motcon2: ip automatic version update 2017-04-14 17:11:08 +03:00
Adrian Costina 4981e6e525 usb_fx3: ip automatic version update 2017-04-14 16:55:30 +03:00
Adrian Costina c419b0042b pluto: ip automatic version update 2017-04-14 16:55:07 +03:00
Adrian Costina 79174422b6 imageon: ip automatic version update 2017-04-14 16:54:42 +03:00
Adrian Costina 4bda0c3a1a cftl_cip: ip automatic version update 2017-04-14 16:54:07 +03:00
Adrian Costina afe8b071a3 cftl_std: ip automatic version update 2017-04-14 16:53:10 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
AndreiGrozav 04a4001dba Ip automatic version update: fmcadc2, fmcadc5 2017-04-12 19:03:16 +03:00
AndreiGrozav 627f78ec19 Ip automatic version update: common/board
- vc707
- zc702
- zed
2017-04-12 19:03:16 +03:00
Istvan Csomortani 3f0633aadc spi_engine: Fix CMD_FIFO_VALID generation
Because of the memory map interface mux, up_waddr_s and up_wreq_s should be
used, when cmd_fifo_in_valid is generated.
2017-04-12 14:57:22 +02:00
Istvan Csomortani ee398b4703 spi_engine: Fix CMD_FIFO_VALID generation
Because of the memory map interface mux, up_waddr_s and up_wreq_s should be
used, when cmd_fifo_in_valid is generated.
2017-04-12 14:43:00 +02:00
Adrian Costina 7c191a089f fmcjesdadc1: Update xcvr configuration to the default one used for this board 2017-04-12 14:41:43 +03:00
Adrian Costina 75409eeb38 util_fir_int: Shifted data so that the amplitude at the output of the filter is the same with the input 2017-04-12 13:49:53 +03:00
Adrian Costina 096aadbf91 util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero
This removes the added DC component that was introduced by the previous rounding mode
2017-04-12 13:49:37 +03:00
Rejeesh Kutty 6d2b3bc1c7 adi_project- try something simple first 2017-04-11 14:27:35 -04:00
Rejeesh Kutty 1d9a8a24dc adi_board- create_bd_cell replacement 2017-04-11 14:26:02 -04:00
AndreiGrozav bc9483c5a2 Ip automatic version: Update ad*/common/ad*_bd.tcl
ad6676evb/common/ad6676evb_bd.tcl
ad7616_sdz/common/ad7616_bd.tcl
ad7768evb/common/ad7768evb_bd.tcl
ad9265_fmc/common/ad9265_bd.tcl
ad9434_fmc/common/ad9434_bd.tcl
ad9467_fmc/common/ad9467_bd.tcl
ad9739a_fmc/common/ad9739a_fmc_bd.tcl
adrv9371x/common/adrv9371x_bd.tcl
adv7511/common/adv7511_bd.tcl
fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 18:52:37 +03:00
Rejeesh Kutty 454e6c0382 daq2- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:53 -04:00
Rejeesh Kutty 2535165461 xilinx- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:19 -04:00
Rejeesh Kutty 80f93e6a31 zc706- ad-ip-instance & ad-ip-parameter 2017-04-06 13:03:22 -04:00
Rejeesh Kutty 820874ef93 adi_board- add auto ip version handling 2017-04-06 13:02:17 -04:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani c637d848bb util_clkdiv: constraints should be applied LATE for this core 2017-04-03 18:14:29 +03:00
Istvan Csomortani e0efbe210e constraints: constraint files should be specified at adi_ip_files 2017-04-03 18:12:28 +03:00
Istvan Csomortani f7190dbbfd adxcvr: Update Makefiles 2017-04-03 12:38:40 +03:00
Istvan Csomortani fa5f81f6c6 axi_dacfifo: Fix clock for read address generation 2017-04-03 10:39:17 +03:00
Istvan Csomortani 7cb7bc111e axi_dacfifo: Delete unused wires 2017-04-03 10:38:50 +03:00
Istvan Csomortani 14b4c4cf5f axi_dacfifo: Define constraint for bypass
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-04-03 10:38:28 +03:00
Istvan Csomortani 06605ed1e1 axi_dacfifo: Register the dac_valid signals 2017-04-03 10:38:09 +03:00
Istvan Csomortani 77081a6233 axi_dacfifo: Data from DMA is validated with dma_ready too 2017-04-03 10:37:45 +03:00
Istvan Csomortani af3a4f5fc9 axi_dacfifo: axi_dvalid should come from dacfifo_rd module 2017-04-03 10:37:30 +03:00
Istvan Csomortani b30041f7f3 axi_dacfifo: Redesign the bypass functionality 2017-04-03 10:37:08 +03:00
Istvan Csomortani 434d1ea52c axi_dacfifo: Fix constraints 2017-04-03 10:36:46 +03:00
Rejeesh Kutty 2f023437b4 adi_ip- remove adi_ip_constraints 2017-04-02 10:42:51 -04:00