Commit Graph

5636 Commits (11822e2824030e49549bab715b9db3c4144447f7)

Author SHA1 Message Date
Istvan Csomortani 5c5baf3abf spi_engine: Fix CMD_FIFO_VALID generation
Because of the memory map interface mux, up_waddr_s should be used,
when cmd_fifo_in_valid is generated.
2017-04-27 11:19:20 +03:00
Istvan Csomortani 29f0ce36bb axi_ad5766: Initial commit
This core can be used in conjunction with the SPI_ENGINE, will work
as an offload module, forwarding a data stream to the SPI excecution,
received from a DMA.
2017-04-27 11:16:23 +03:00
Istvan Csomortani d177827224 ad5766_sdz : Fix SPI interface connection 2017-04-27 11:16:23 +03:00
Istvan Csomortani fb6e0d3efb spi_engine: Add dependency for unused interfaces 2017-04-27 11:16:19 +03:00
Istvan Csomortani 225d133a68 ad5766_sdz: Initial commit 2017-04-27 11:12:45 +03:00
Rejeesh Kutty 5d6b018b2b ad9162- add iq swap 2017-04-26 20:54:47 -04:00
Istvan Csomortani 85a647eda8 axi_ad9361: Fix ad_cmos_out instantiations
This is a patch for 3627b89
2017-04-26 10:39:54 +03:00
Adrian Costina 7cff12107e hdlmake: Fix util_clkdiv Makefile issue. sort library master Makefile 2017-04-26 09:58:17 +03:00
Rejeesh Kutty cfd4e006b3 hdlmake updates 2017-04-25 15:46:26 -04:00
Rejeesh Kutty 8fba8295f0 fmcadc5- hdl sync handling 2017-04-25 15:44:40 -04:00
Rejeesh Kutty 68bb7ffa40 adi_board- keep port delete simple 2017-04-25 15:44:03 -04:00
Rejeesh Kutty 804df251a6 axi_fmcadc5_sync- updates 2017-04-25 11:35:37 -04:00
Rejeesh Kutty 81570ada75 axi_fmcadc5_sync- updates 2017-04-25 11:35:37 -04:00
Rejeesh Kutty c248d5ac6a fmcadc5-sync- try sync in hdl 2017-04-25 11:35:37 -04:00
Istvan Csomortani 8eb65186e9 cn0363: Reorder the configuration settings of the fir filters
It seems that there are some dependencies between the fir compiler
cores parameters. With the old order of the parameter settings,
the tool throws the following warning:

CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES
does not match between /processing/sequencer/i_q_filtered(4)
and /processing/lpf/M_AXIS_DATA(5)
2017-04-25 17:40:09 +03:00
Istvan Csomortani 468965a792 altera/ad_cmos_in: Define supported DEVICE_TYPE options 2017-04-25 12:07:33 +03:00
Istvan Csomortani 52305f74c8 altera/ad_cmos_in|out: Delete redundant parameter 2017-04-25 12:06:33 +03:00
Istvan Csomortani 77eafbcccd avl_dacfifo: Update constarint file 2017-04-25 12:03:46 +03:00
Istvan Csomortani 1ef3fd4668 avl_dacfifo: Fix read/write address switching 2017-04-25 12:03:22 +03:00
Istvan Csomortani 3627b892c3 xilinx/ad_cmos_in|out: Delete redundant parameter
The LVCMOS standard is a single ended IO standard. The SINGLE_ENDED
parameter is redundant in this case.
2017-04-25 11:02:35 +03:00
Adrian Costina a6457cb54f m2k:standalone, remove power optimizations as they are performed manually
- testing shows that the actual power consumtion is a bit less with them turned off
2017-04-25 10:09:55 +03:00
Istvan Csomortani b92703b59f daq2: Fix typo 2017-04-24 15:44:45 +03:00
Istvan Csomortani 0cfef974a6 cn0363: Fix typos and mistakes made in 0737183 2017-04-24 12:43:33 +03:00
Istvan Csomortani b9bc85dd1a daq2/zcu102: Update tcl command for IP configuration 2017-04-24 11:51:12 +03:00
Istvan Csomortani 871cfa7e5b daq2/kcu105: Update tcl command for IP configuration 2017-04-24 11:50:35 +03:00
Istvan Csomortani 49f096dc71 daq1: Fix typo 2017-04-24 11:49:08 +03:00
Istvan Csomortani 4e77acf282 adv7511/kcu105: Update tcl command for IP configuration 2017-04-24 11:48:33 +03:00
Istvan Csomortani 4f4ca84813 axi_dacfifo: Fix Makefile 2017-04-24 11:46:29 +03:00
Istvan Csomortani 4007df2094 avl_dacfifo: Update constraints 2017-04-21 17:25:46 +03:00
Istvan Csomortani 89b3f45fff avl_dacfifo: Use the ad_mem_asym for altera 2017-04-21 17:25:46 +03:00
Istvan Csomortani b7bfa2d91f avl_dacfifo: Delete redundant file 2017-04-21 17:25:46 +03:00
Lars-Peter Clausen 216826a9e5 adv7511: audio_clkgen: Disable clock source buffer insertion
Depending on the configuration of the clock source type of the input clock
the clocking wizard will instantiate all kinds of buffers on the input
clock signal.

For these particular projects there is no need to add any kind of buffer
since the source is already coming from a global clock buffer.  So set the
configuration accordingly.

Avoids the following warning:
	[Opt 31-32] Removing redundant IBUF since it is not being driven by a
	top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg
	Resolution: The tool has removed redundant IBUF. To resolve this
	warning, check for redundant IBUF in the input design.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 14:21:27 +02:00
Lars-Peter Clausen 4a582bf9ad adv7511: audio_clkgen: Disable phase alignment
There is no need for the audio clock to be phase aligned to its source
clock. When phase alignment is disabled the MMCM uses an internal feedback
path without requiring external resources, so disable it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 14:21:27 +02:00
Lars-Peter Clausen 76e4105bfd adv7511: audio_clkgen: Infer input clock frequency
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 14:21:27 +02:00
Lars-Peter Clausen a12adf9f02 adv7511: audio_clkgen: Disable unused pins
Neither the reset nor the locked signal is used in this design, so disable them. Avoids warnings about unconnected pins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 14:21:27 +02:00
Istvan Csomortani 74687eb88b fmcomms7: Update IP instantiations 2017-04-21 15:12:01 +03:00
Istvan Csomortani 5174bc1f67 fmcomms11: Update IP instantiations 2017-04-21 15:11:25 +03:00
Istvan Csomortani c9eaa43b1e fmcomms5: Update UP instantiations 2017-04-21 15:10:44 +03:00
Istvan Csomortani bb0cdf2f5e fmcomms2: Update IP instantiations 2017-04-21 15:09:37 +03:00
Istvan Csomortani 95249d2165 fmcjesdadc1: Update IP instantiations 2017-04-21 15:08:16 +03:00
Istvan Csomortani 4eaa43f8e1 daq3: Update IP instantiations 2017-04-21 15:07:41 +03:00
Istvan Csomortani 1ae357ce10 daq1: Update IP instantiations 2017-04-21 15:06:40 +03:00
Istvan Csomortani 073718315a cn0363: Update IP instantiations 2017-04-21 15:06:06 +03:00
Istvan Csomortani fa794520fd kc705_common/adv7511: Update IP instantiations 2017-04-21 15:03:31 +03:00
Lars-Peter Clausen 0e6cc95d0d pzsdr1/pzsdr2: audio_clkgen: Disable clock source buffer insertion
Depending on the configuration of the clock source type of the input clock
the clocking wizard will instantiate all kinds of buffers on the input
clock signal.

For these particular projects there is no need to add any kind of buffer
since the source is already coming from a global clock buffer.  So set the
configuration accordingly.

Avoids the following warning:
	[Opt 31-32] Removing redundant IBUF since it is not being driven by a
	top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg
	Resolution: The tool has removed redundant IBUF. To resolve this
	warning, check for redundant IBUF in the input design.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 13:22:33 +02:00
Lars-Peter Clausen 95a46bf1e1 pzsdr1/pzsdr2: audio_clkgen: Disable phase alignment
There is no need for the audio clock to be phase aligned to its source
clock. When phase alignment is disabled the MMCM uses an internal feedback
path without requiring external resources, so disable it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 13:22:33 +02:00
Lars-Peter Clausen cfc51016ea pzsdr1/pzsdr2: audio_clkgen: Infer input clock frequency
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 13:22:19 +02:00
Istvan Csomortani 6ed721ee66 adrv9371/a10soc: Integrate the avl_dacfifo into project 2017-04-21 13:27:35 +03:00
Istvan Csomortani 180a80493b avl_dacfifo: Initial commit 2017-04-21 13:26:37 +03:00
Istvan Csomortani 5fe7a1b100 axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass 2017-04-21 13:23:03 +03:00