Commit Graph

18 Commits (11822e2824030e49549bab715b9db3c4144447f7)

Author SHA1 Message Date
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Istvan Csomortani 5a257ce3c5 fmcomms5: Delete unused GPIO lines from system top
In the system top of the FMCOMMS5 projects, there are several GPIO lines, which
can not find in the constraint file, respectively gpio_open_15_15,
gpio_open_44_44 and gpio_45_45.

These are floating GPIO pins, as their names suggest. Delete all these wires and
update IOBUF instances.
2018-05-30 09:55:04 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Adrian Costina 98b58562d6 system_top: Non functional changes in system_tops to reduce warnings
Loop back the unused GPIO pins, and add all the SPI interface to system
wrapper instance.

The following system_top modules were changed:
  - ad738x_fmc
  - ad7616_sdz
  - ad77681evb
  - ad77681evb
  - ad7768evb
  - ad9739a_fmc
  - ad9434
  - adrv9739
  - fmcadc5
  - ad6676evb
  - ad9265
  - ad5766
  - fmcomms5
  - m2k
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 271731ebc8 fmcomms5: Remove wires that are redeclarations of ports
Fixes the following warnings:
	[Synth 8-2611] redeclaration of ansi port txnrx_0 is not allowed
	[Synth 8-2611] redeclaration of ansi port enable_0 is not allowed
	[Synth 8-2611] redeclaration of ansi port enable_1 is not allowed
	[Synth 8-2611] redeclaration of ansi port txnrx_1 is not allowed

This is a leftover of commit 1c23cf4621 ("all: Update verilog files to
verilog-2001").

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-16 13:32:26 +01:00
Rejeesh Kutty 6cee492d96 fmcomms5/zc702- pmods as gpios 2017-08-09 14:07:58 -04:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
AndreiGrozav 3bc9df4c51 fmcomms5: Fixed the wornings created by TDD missing connections to axi_ad9361 core 2016-12-07 21:43:19 +02:00
Rejeesh Kutty a6cae6b477 iobuf: do is a system verilog keyword 2015-05-21 14:06:17 -04:00
Adrian Costina e58e9bc701 fmcomms5: Updated zc702 project to the latest framework 2015-03-31 17:44:09 +03:00
Adrian Costina 0ade2a5f67 fmcomms5: Updated project to vivado 2014.2. Updated interrupt system. Fixed constraints 2014-11-07 13:45:15 +02:00
Adrian Costina 9cdd4107cd fmcomms5: ZC702: add reset_b and fixed system_top 2014-07-25 15:24:11 +03:00
Rejeesh Kutty 9a36075324 moved fmcomms5 2014-05-19 13:49:49 -04:00