Note, the current SCLK to spi_clk ratio is four. That means, the input
delay in the MISO line is 25% of the SCLK period.
If the SCLK to spi_clk ratio is changing, this constraint must be
updated.
Generate a higher frequency of spi_clk using an axi_clkgen. (MMCM)
CAUTION: ad7768-1 is still violating the standard SPI timing,
reducing the timing window significantly for the last bit (or last high
bit).
Istvan Csomortani
Sergiu Arpadi
Stanca Pop