Sergiu Arpadi
|
d8ab27b2af
|
sysid: Remove cstring init string
|
2020-09-30 19:12:24 +03:00 |
|
Arpadi
|
0680e44330
|
system_id: deployed ip
|
2019-08-06 16:53:11 +03:00 |
Istvan Csomortani
|
7960b00684
|
block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
|
2019-06-11 18:13:06 +03:00 |
Laszlo Nagy
|
b98eb28dca
|
adrv9371: update adcfifo/dacfifo
|
2019-01-23 14:45:45 +02:00 |
Michael Hennerich
|
2e59a70cdd
|
adrv9371: Increase FCLK2 to 200MHz to support max sampling rates
This fixes an issue seen when using 307.2 MSPS on the Observation RX.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
|
2018-01-09 15:20:06 +01:00 |
AndreiGrozav
|
a64998c3ff
|
adrv9371x: Separate ps7 assignaments from common
Move the assignaments/connections for ps7 from common/adrv9371_bd
to zc706/system_bd
|
2017-08-22 15:37:59 +03:00 |
Rejeesh Kutty
|
fb4a583613
|
projects/system_bd- adc/dac fifo board designs
|
2017-02-27 16:06:39 -05:00 |
|
Rejeesh Kutty
|
edd5e9570f
|
file renamed; sed output; fingers crossed
|
2017-02-22 15:56:37 -05:00 |
|
Rejeesh Kutty
|
ce1fed1ce6
|
dmafifo- adc/dac split
|
2016-08-16 12:54:39 -04:00 |
|
Istvan Csomortani
|
3859cba186
|
adrv9371x/zc706: Add PL_DDR FIFO to the design
|
2016-05-27 14:13:55 +03:00 |
|
Rejeesh Kutty
|
f92e8509bb
|
adrv9371x- added
|
2016-05-20 11:46:25 -04:00 |