2379514ae6
ac701_common/adv7511: Update IP instantiations
...
IPs are instantiated using the ad_ip_instance process, and configured
with the ad_ip_paramter process, to facilitate the tool upgrade.
2017-04-21 13:16:25 +03:00
bb0021a926
common: zed/zc702/zc706/mitx045: audio_clkgen: Disable phase alignment
...
There is no need for the audio clock to be phase aligned to its source
clock. When phase alignment is disabled the MMCM uses an internal feedback
path without requiring external resources, so disable it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
bfcc3696e4
common: zed/zc702/zc706/mitx045: Set audio clkgen clock source type
...
Depending on the configuration of the clock source type of the input clock
the clocking wizard will instantiate all kinds of buffers on the input
clock signal.
For these particular projects there is no need to add any kind of buffer
since the source is already coming from a global clock buffer. So set the
configuration accordingly.
Avoids the following warning:
[Opt 31-32] Removing redundant IBUF since it is not being driven by a
top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg
Resolution: The tool has removed redundant IBUF. To resolve this
warning, check for redundant IBUF in the input design.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
23ccc66f22
common: zc702/zc706/mitx045: audio_clkgen: Infer input clock frequency
...
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
b213567305
common: zed: audio_clkgen: Infer input clock frequency
...
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 16:29:09 +02:00
71394ee465
kcu105: ip automatic version update
2017-04-18 11:59:54 +03:00
942d69a30c
Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
2017-04-18 10:57:16 +03:00
20672a3a8b
mitx045: ip automatic version update
2017-04-14 17:46:25 +03:00
954037a716
microzed: ip automatic version update
2017-04-14 17:24:24 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
627f78ec19
Ip automatic version update: common/board
...
- vc707
- zc702
- zed
2017-04-12 19:03:16 +03:00
2535165461
xilinx- ad-ip-instance & ad-ip-parameter
2017-04-06 13:04:19 -04:00
80f93e6a31
zc706- ad-ip-instance & ad-ip-parameter
2017-04-06 13:03:22 -04:00
deb8635854
adrv9371x/altera- gpio equivalency fix
2017-03-27 16:37:55 -04:00
4a275302a0
a5soc- add ddr3 location assignments
2017-03-22 10:12:34 -04:00
b3f06af77a
altera srf files do not work
2017-03-22 09:25:50 -04:00
66a5d44a18
a5gte- add constraints for tq
2017-03-21 10:53:31 -04:00
2e22ce3b62
a10gx- ignore preliminary timing model warnings
2017-03-21 10:52:28 -04:00
c7351f3ce3
arradio/c5soc- remove qsys files
2017-03-20 15:56:07 -04:00
589e6b53d8
arradio/c5soc- qsys-script flow
2017-03-20 15:42:33 -04:00
b39fecadd9
altera- ignore preliminary timing messages
2017-03-20 12:48:53 -04:00
7dfa8c599f
arradio/c5soc- updated to new framework/16.0
2017-03-20 12:15:18 -04:00
12f44ccbcc
arradio/c5soc- critical warnings fix
2017-03-20 12:14:21 -04:00
3fa9a30f0e
a10soc/plddr4- lower mem clk to meet timing
2017-03-06 14:12:25 -05:00
38a27d02f6
a10soc/plddr4- differential refclk
2017-03-06 14:11:36 -05:00
ec89b1a45f
altera/adrv9371x- add dacfifo
2017-03-01 15:52:07 -05:00
c1be17a3af
Altera a10 devices: disable warnings regarding unused channels
2017-03-01 11:32:17 +02:00
aad41039bd
a10soc- plddr4 settings
2017-02-28 13:36:28 -05:00
c1aac4a9fb
common: adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
b00dc4b195
plddr3- change to board files
2017-02-22 15:22:50 -05:00
89b49d2f67
fifo- as board files
2017-02-22 15:18:50 -05:00
879ed64bb6
compression flag changes
2017-02-22 15:15:53 -05:00
754ac6a403
w/r-fifo- removed
2017-02-22 15:10:06 -05:00
a15e05c497
adcfifo- remove axi-byte-width parameter
2017-02-17 15:29:10 -05:00
cb3d1883bc
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
2017-02-17 15:21:33 -05:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
c39ed08edd
zcu102/*- actual clock == desired clock
2017-02-06 12:53:47 -05:00
be1328c55b
kcu105- added missing ethernet configurations
2017-01-23 10:14:09 -05:00
18660c7ab4
fmcjesdadc1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
1ceec2e2a9
projects/a5gt- use 50m afi clock for cpu- xcvr reconfig timing
2016-12-22 14:14:21 -05:00
eba30b0cde
projects/altera- qii_auto_pack option
2016-12-22 14:14:21 -05:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
9fb7db97da
a5gte: Fixed timing violations
2016-12-13 10:30:24 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
8e69c838e1
common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND
2016-12-09 13:54:39 +02:00
fb287d0178
kcu105- updates to match xilinx trd
2016-12-08 09:32:33 -05:00
4739d05269
zc706pr/common- removed
2016-11-18 14:52:39 -05:00
f43248c2bc
common/pzsdr*- removed
2016-11-18 11:32:43 -05:00
959055bd54
common/a5gt- updates
2016-11-10 16:56:35 -05:00
c6730ab2d7
fmcjesdadc1/a5gt- updates
2016-11-10 11:36:41 -05:00
8af0731bb0
a5gt- qsys2tcl flow
2016-11-10 11:30:18 -05:00
3cc416ca60
pzsdr1- fix typo on system_ps7
2016-11-09 12:04:30 -05:00
f0af8216ce
common/a5soc- device can not run at 100M cpu clock
2016-11-08 15:19:23 -05:00
d9cfccc05f
common/a5soc- gpio in/out separation
2016-11-08 15:19:02 -05:00
6b492b79db
a10soc - remove default assignments
2016-11-04 15:01:19 -04:00
8ea9beffaf
fmcjesdadc1- a5soc tcl updates
2016-11-04 15:01:19 -04:00
4e99c3be9a
a5soc- tcl flow updates
2016-11-04 15:01:19 -04:00
50552ce7d6
adrv9371x- altera updates
2016-10-27 09:25:00 -04:00
f752f0c9d7
a10soc- xcvr updates
2016-10-27 09:25:00 -04:00
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
721ee98a06
zcu102- misc fixes
2016-10-06 10:18:14 -04:00
baabe20766
common/zcu102- spi connections & clock
2016-10-05 14:01:59 -04:00
9afff7ae60
common/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
e40311eee9
adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz
2016-09-29 09:14:37 +01:00
4239f64125
dacfifo- board pin warnings
2016-09-27 14:49:20 -04:00
751a66eb72
plddr3/zc706- board pin warning
2016-09-26 15:20:37 -04:00
2d307d5f58
a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design
2016-09-24 10:06:35 +03:00
14ad1ea741
pzsdr- swap clear-up
2016-09-21 13:15:40 -04:00
143423e3b9
adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera
2016-09-21 18:13:02 +03:00
cf9ac730a8
pzsdr1- new rev. board delays
2016-09-13 10:32:13 -04:00
40c9fc92c1
a10soc: Switched to tcl flow
2016-09-08 11:31:06 +03:00
0d095f5da9
a10gx: Added system_type variable in common design
2016-09-08 11:29:14 +03:00
b837883b98
pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed voltage level selection
2016-09-01 17:16:59 +03:00
917da79da1
altera- source defaults for qsys-script
2016-08-30 11:50:36 -04:00
8192e755e1
altera- defaults
2016-08-30 11:50:36 -04:00
2e59f377e1
version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
2016-08-29 09:50:46 +03:00
271029768c
pzsdr/cmos - swap==1
2016-08-26 10:31:00 -04:00
5cc2ab37a5
version_upgrade: Common ZC702 get an upgrade to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 10:20:04 +03:00
c6b065c349
zc706: Updated DDR3 dacfifo
2016-08-22 16:48:52 +03:00
5d0e08d92e
common/vc707- 2016.2 version
2016-08-17 10:36:19 -04:00
73413366bc
daq2/all - warnings fix
2016-08-17 10:36:00 -04:00
0694a5015d
kc705- 2016.2 version
2016-08-16 12:54:39 -04:00
8464816c82
dmafifo-split to adc/dac
2016-08-16 12:54:39 -04:00
4658686ae1
adrv9371x/a10soc: Misc changes for being able to run Linux
2016-08-16 11:56:25 +03:00
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
16ad0f4379
kcu105- 2016.2 update
2016-08-11 10:00:41 -04:00
285059aed0
kcu105: Don't use phy reset automation, as it's not supported for KCU105
2016-08-09 10:19:57 +03:00
452d4706d3
kcu105: Update base project to 2015.4.2
...
- change part to revision 1.1 of the board
2016-08-09 10:19:36 +03:00
c6f4def93d
altera- make mmu a make switch
2016-08-08 11:54:51 -04:00
418217dd10
pzsdr: Remove LED and button signals from PCIe carrier
...
Only the FMC carrier and the breakout board do have push buttons and LEDs.
They are not present on the PCIe carrier. So move the constraints to a
separate file that can be included by the projects that need them and
remove all LED and button related signals from the PCIe project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
52ae3ddd6c
a10gx: Updated common files to 16.0
2016-08-01 15:08:12 +03:00
9952a94efb
hdl-vivado-2016.2- ip version updates
2016-07-28 13:44:57 -04:00
62c7114d77
Enable bitstream compression for Xilinx projects
...
Enabling bitstream compression reduces the size of the generated bitstream.
This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.
On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.
The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.
When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.
Initial tests show a reduction of a round 50% in size for most ADI
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:16:15 +02:00
c6c3622816
a10gx: Updated common design adding explicit clock frequency and synchronous reset deassertion
2016-06-30 10:59:29 +03:00
2e80dec513
adrv9371x/zc706: Update project with the new axi_dacfifo
2016-06-22 12:33:47 +03:00
eaf4d4a19d
makefile updates
2016-06-10 14:26:14 -04:00
625052f46e
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina
AndreiGrozav
Rejeesh Kutty
dbogdan
Shrutika Redkar