25e42c49d6
library: move alt cores to common
2017-05-26 10:51:25 -04:00
10898d6618
constraints: Split the regmap CDC constraint into separate file
2017-05-25 15:12:16 +03:00
cb8d6830f5
avl_dacfifo: Update constraints
2017-05-25 15:12:16 +03:00
3ee7ed7375
avl_dacfifo: Cosmetic changes
2017-05-25 15:12:15 +03:00
154e936a4b
avl_dacfifo: Fix issues with avl_dacfifo_wr
...
+ fix issues with the last partial avalon transfer.
+ fix reset related problems
2017-05-25 15:12:15 +03:00
e34e87e7f8
avl_dacfifo: Add support for partial avalon transfers
...
By adding support for partial avalon transfers (data width < bus width),
valid data set size (DMA transfer length) will be dependent on the DMA bus
width only.
2017-05-25 15:12:15 +03:00
a993eefe57
avl_dacfifo: Grey coder/decoder integration
2017-05-25 15:12:14 +03:00
14a058195d
avl_dacfifo: Add avl_dacfifo_byteenable_coder
...
Define and integrate avl_dacfifo_byteenabke_coder module,
which generates the byteenable signal for the avalon interface.
2017-05-25 15:12:14 +03:00
81fa65cd51
avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
...
+ avl_write_transfer_done_s is a redundant net
+ specify the net state explicitly on if statements
+ to define the edge of avl_mem_fetch_wr_address signal,
its register and its second sync register should be used
2017-05-25 15:12:13 +03:00
398619d866
avl_dacfifo: Add support for MEM_RATIO 32
2017-05-25 15:12:13 +03:00
a1539a62b7
avl_dacfifo: Integrate util_delay into dac_xfer_out path
...
The ad_mem_asym memory read interface has a 3 clock cycle delay, from the
moment of the address change until a valid data arrives on the bus;
because the dac_xfer_out is going to validate the outgoing samples (in conjunction
with the DAC VALID, which is free a running signal), this module will compensate
this delay, to prevent duplicated samples in the beginning of the
transaction.
2017-05-25 15:12:13 +03:00
6d52034abb
avl_dacfifo: dma_ready was muxed incorrectly
2017-05-25 15:12:12 +03:00
da68705fee
avl_dacfifo: Fix the avalon address switch
2017-05-25 15:12:12 +03:00
04f397f688
avl_dacfifo: Fix a few control signals
...
+ avl_last_transfer depends on the avl_xfer_req state
+ avl_xfer_req will be asserted after the last avalon write
transfer
2017-05-25 15:12:12 +03:00
8f9cadb017
avl_dacfifo: Fix the avl_write generation
...
The asymetric memory has a 3 clock cycle delay on its read
interface, therefor the minimum distance between two consecutive
avalon write should be 3.
2017-05-25 15:12:11 +03:00
0f1e51ac98
avl_dacfifo: Fix alv_mem_readen generation
2017-05-25 15:12:11 +03:00
f456ebc6f0
avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
...
+ all net names should have a *_s postfix
+ avl_burstcount is a constant 1, no need for an additional
register for it
+ all CDC should have two synchronization register, add
avl_last_beat_req_m2
2017-05-25 15:12:11 +03:00
9a6dc36289
avl_dacfifo: Fix indentation for acl_dacfifo.v
2017-05-25 15:12:10 +03:00
7666c9f0d2
avl_dacfifo: Add a parameter AVL_ADDRESS_WIDTH
2017-05-25 15:12:10 +03:00
6dbbe2f1ca
altera/ad_mem_asym: Fix grounded bus for marco instance
...
The "'b0" constant will be translate as a 32 bit width vector by
ModelSim, and will throw a buswidth mismatch error. Tie the data_b
bus to zero, using its width parameter.
2017-05-25 15:12:09 +03:00
80a3f45b9f
alt_mul- qsys replacement
2017-05-18 10:38:48 -04:00
6649b23bc8
alt-mem-asym - replace mega function cores
2017-05-17 16:13:26 -04:00
bea72232a3
alt_mem_asym- qsys component
2017-05-17 16:13:26 -04:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
c728299e71
altera- default to latest version
2017-05-12 13:25:17 -04:00
468965a792
altera/ad_cmos_in: Define supported DEVICE_TYPE options
2017-04-25 12:07:33 +03:00
52305f74c8
altera/ad_cmos_in|out: Delete redundant parameter
2017-04-25 12:06:33 +03:00
77eafbcccd
avl_dacfifo: Update constarint file
2017-04-25 12:03:46 +03:00
1ef3fd4668
avl_dacfifo: Fix read/write address switching
2017-04-25 12:03:22 +03:00
4007df2094
avl_dacfifo: Update constraints
2017-04-21 17:25:46 +03:00
89b3f45fff
avl_dacfifo: Use the ad_mem_asym for altera
2017-04-21 17:25:46 +03:00
b7bfa2d91f
avl_dacfifo: Delete redundant file
2017-04-21 17:25:46 +03:00
180a80493b
avl_dacfifo: Initial commit
2017-04-21 13:26:37 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
3586397f57
altera/common- add asymmetric fifo
2017-03-01 15:35:04 -05:00
0dae754f2d
axi_adxcvr: Add rparam register to Altera XCVR
2017-02-10 16:19:17 +02:00
db924953bb
altera- warnings about init values
2017-01-30 10:01:28 -05:00
c0a2ef1ac4
library- altera power up warnings
2016-12-20 16:18:15 -05:00
0715c962f1
altera/ad_serdes: Fix net alignment for rx_out at ad_serdes_in
2016-12-06 15:24:19 +02:00
6cf9df50e3
altera/ad_serdes: Define DEVICE_FAMILY in hw script
2016-12-06 15:24:18 +02:00
0b58a2a1db
avl_adxcvr- sysclk frequency
2016-11-09 09:21:07 -05:00
48ee720901
avl_adxcvr- a5 requires single transceiver controller
2016-11-08 15:20:01 -05:00
ee9c8b884d
avlxcvr- add arria v support
2016-11-04 15:01:19 -04:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
9f4c5f8060
arradio/ad9361- updates
2016-10-31 15:34:32 -04:00
b94cc8afb1
altera- cmos cores
2016-10-31 13:13:48 -04:00
e0459df0f3
altera -c5 qsys alternative
2016-10-31 11:18:27 -04:00
cc75fa3dfe
altera- java/tcl mess handling
2016-10-31 10:54:07 -04:00
a9d03af771
altera- serdes changes
2016-10-28 14:09:18 -04:00
8107514dde
altera/common- ad_serdes_clk
2016-10-27 09:41:10 -04:00
6f611e0d10
altera/alt_serdes: Add support for Cyclone V
2016-10-25 20:32:51 +03:00
707038937a
alt_serdes: Add additional parameters
...
Add additional parameters to keep the top of ad_serdes_* modules
consistant through differente carriers.
2016-10-24 11:42:43 +03:00
2d93d787ab
altera/ad_cdfilter: Update interface to Verilog 2001 standard
2016-10-11 17:59:21 +03:00
ae47895666
altera/alt_serdes: Fixed SERDES 4 factor initialization
2016-10-11 17:59:17 +03:00
d41945f568
altera/ad_serdes: Add support for any SERDES factor less than 8
2016-10-11 17:59:14 +03:00
6510f92c12
ad_serdes : Cosmetic changes
2016-09-16 14:45:39 +03:00
13a35f7a2a
altera/ad_serdes_clk: The IO_PLL reset is active heigh
2016-09-16 14:20:39 +03:00
858ea09048
altera/ad_serdes_in: Fix some typos
2016-09-16 10:56:16 +03:00
a2d15acb89
ad_serdes- altera/xilinx sync
2016-09-15 13:33:55 -04:00
63696c1a28
alt_serdes- data-width parameter
2016-09-15 11:12:18 -04:00
02dfd2d2e2
altera/ad_serdes_out- sample transmit order
2016-09-15 10:28:34 -04:00
5986f45cba
altera/ad_serdes_out- updates
2016-09-15 09:38:11 -04:00
fe133a7c39
v2001- parameter defines
2016-09-14 15:47:45 -04:00
16046a984c
alt_serdes- updates
2016-09-14 12:05:48 -04:00
4a6b554c0a
ad_serdes- updates
2016-09-14 11:12:53 -04:00
a0318ae868
ad_serdes_clk- syntax errors
2016-09-13 14:02:11 -04:00
734b39a8ed
alt_serdes: Fix some issues in the _hw.tcl script
2016-09-13 17:42:51 +03:00
73ebf1225c
axi_adxcvr- ip/phy split
2016-09-12 14:57:50 -04:00
21545ee83f
avl_adxcvr- ip/phy split
2016-09-12 14:57:50 -04:00
8718b7f477
avl_adxphy- ip/phy split
2016-09-12 14:57:50 -04:00
d30ffdb7e9
avl_adxcfg- ip/phy split
2016-09-12 14:57:50 -04:00
9159e31244
axi_adxcvr- compile fixes
2016-09-12 14:57:50 -04:00
5a309d8863
avl_adxphy- split
2016-09-12 14:57:50 -04:00
2a34f9baa8
alt-serdes, in & out
2016-09-12 11:45:23 -04:00
9e0c39a71b
alt_serdes_clk- changes
2016-09-12 10:30:28 -04:00
f4be0524b4
altera/common: Add SERDES related modules
2016-09-09 18:04:41 +03:00
4ae084ee32
avl_adxcvr- compile fixes
2016-09-01 10:06:28 -04:00
5544e3cf10
axi_adxcvr- compile fixes
2016-09-01 10:06:28 -04:00
230f1526c0
avl_adxcfg- compile fixes
2016-09-01 10:06:28 -04:00
b7ea2efa87
altera- xcvr cores
2016-08-29 15:18:48 -04:00
6a8ca8107a
common: Added common ad_dcfilter stub for altera.
2016-08-16 17:37:16 +03:00
90ac7b7ac9
lib_refactoring: Move all Altera module to library/altera/common
...
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
2016-08-08 15:07:01 +03:00
cb9af99c5d
lib_refactoring: Add ad_mul.v for Altera
2016-08-08 15:06:48 +03:00
5faf4c4976
cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them
2016-08-05 16:27:52 +03:00
2b7c976be5
xcvr- altera/xilinx split
2016-08-04 13:26:10 -04:00
Rejeesh Kutty
Istvan Csomortani
AndreiGrozav
Adrian Costina