Commit Graph

1542 Commits (0e5a24ee7cab98020358b3360b8ed1f14395aa55)

Author SHA1 Message Date
Rejeesh Kutty 3f00614bc7 axi_jesd_xcvr: rx/tx only select 2016-05-20 16:13:36 -04:00
Rejeesh Kutty f1a603a3b1 ad9371- altera ip 2016-05-20 15:16:36 -04:00
Rejeesh Kutty 09520709b0 make updates 2016-05-20 12:35:45 -04:00
Rejeesh Kutty b5b05bb9d1 axi_ad9371: added 2016-05-20 11:41:54 -04:00
Rejeesh Kutty bf0b90229a rfifo/wfifo- qsys ip 2016-05-18 13:24:13 -04:00
Rejeesh Kutty 7fdaee186c upack/cpack- qsys ip 2016-05-18 13:24:13 -04:00
Rejeesh Kutty a262eb7ab3 ad9361- output-rst - associated-rst issue? 2016-05-18 13:24:13 -04:00
Rejeesh Kutty e15893444c upack- fix interface names 2016-05-18 13:24:13 -04:00
Rejeesh Kutty 285cbc7225 xfifo- fix sdc/xdc names 2016-05-18 13:24:13 -04:00
Rejeesh Kutty d7f0bd1b76 ad9361- add reset sink 2016-05-18 13:24:13 -04:00
Rejeesh Kutty bb4ed42a93 ad9361- add missing wires 2016-05-18 13:24:13 -04:00
AndreiGrozav 42b0fabd40 axi_hdmi_tx_core: Fixed data path 2016-05-17 14:41:18 +03:00
Rejeesh Kutty 68329de738 ad9361- interface updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 421c0519f4 util_rfifo- updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty e05204a86d util_cpack: interface updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 6bc05fc844 ad_*_in: register post-iob 2016-05-16 12:19:38 -04:00
Rejeesh Kutty cd7c9c99ed ad_*_clk: altera-pll not supported by qsys flow 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 4fbff45e27 util_wfifo- updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty f515885fc4 util_wfifo: altera ip 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 58a2a3259c util_rfifo: updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 82d43783f1 util_rfifo: altera ip 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 31671bf9d5 util_rfifo: constraints 2016-05-16 12:19:38 -04:00
Rejeesh Kutty aadb220a3f zcu102- updates 2016-05-10 15:40:41 -04:00
Rejeesh Kutty 3871d3ce2b ad9361-c5/a10 - updates 2016-05-09 13:54:08 -04:00
Rejeesh Kutty 9cd6e2da51 quartus-mess- altddio direct instantiation 2016-05-09 13:54:08 -04:00
AndreiGrozav 726ddb6e93 ad_lvds_clk: Fixed assignment mismatched 2016-05-09 10:32:18 +03:00
Istvan Csomortani b0538a03a2 Make: Update 2016-05-06 16:44:24 +03:00
AndreiGrozav b36c722ec9 up_hdmi_tx: Discard the standard default values
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
2016-05-05 13:41:46 +03:00
AndreiGrozav 68d83def01 axi_hdmi_tx_core: Fixed data path 2016-05-05 13:32:25 +03:00
AndreiGrozav 0d2dc2c62b axi_hdmi_tx: Fixed data bus width 2016-05-05 13:26:59 +03:00
Rejeesh Kutty bdfa383622 library/axi_ad9361: tdd false paths 2016-05-04 13:42:12 -04:00
Rejeesh Kutty ef6c99ecab library/axi_ad9361: hw component updates 2016-05-04 13:42:12 -04:00
Rejeesh Kutty 3b5e44e37d library/axi_ad9361: mmcm rst for plls 2016-05-04 13:42:12 -04:00
Rejeesh Kutty 16a13b2023 library/axi_ad9361: add rst/locked to clock 2016-05-04 13:42:11 -04:00
Rejeesh Kutty 1aac44b0d9 library: ad_*clk- rst/locked 2016-05-04 13:42:11 -04:00
Rejeesh Kutty d82ca5dc3c library/common- altera variations 2016-05-04 13:42:11 -04:00
AndreiGrozav b6b68e9ab7 axi_jesd_gt: Split the constraint file
-split axi_jesd_gt_constr.xdc file in rx, tx and common constraint files
-updated tcl script
2016-05-04 19:32:06 +03:00
István Csomortáni 583bafd17a axi_ad7616: Add a new register for IF_TYPE
Add an additional new read only register at 0x03 address for the interface type. This way the software can verify the actual interface mode.
2016-05-04 16:14:29 +03:00
Rejeesh Kutty 385ed31a45 make files update 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 3f5e1e1203 ad9361- dev_if module name change 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 89f5d2394e altera- clock variations 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 243d3e6e41 ad9361- a10soc sdc files 2016-04-29 10:17:35 -04:00
Rejeesh Kutty aa2aa902bf ad9361- a10soc updates 2016-04-29 10:17:35 -04:00
Rejeesh Kutty f411d29e30 ad9361- a10soc changes 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 3563c2212c common/altera- removed dcfilt/mul 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 0260280db1 common/altera- data path 2016-04-29 10:17:35 -04:00
Rejeesh Kutty ed62101308 common/altera: primitives 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 779d014750 ad9361-common alt/xil interface 2016-04-29 10:17:35 -04:00
Istvan Csomortani 7ec4c00f9f axi_ad7616: DMA is always ready 2016-04-29 16:36:33 +03:00
Istvan Csomortani 427f85959c axi_ad7616: Fix the AXI stream interface 2016-04-29 16:34:34 +03:00
Istvan Csomortani 33199263e1 axi_ad7616: Delete burst_length register
This was an unnecessary feature of the hdl core.
2016-04-29 16:28:48 +03:00
Istvan Csomortani d5d7c12f0e axi_ad7616: Fix the register map 2016-04-25 11:36:39 +03:00
Istvan Csomortani 2ccdd426ec axi_ad7616: Fix the rd_db_valid generation and do some cosmetic changes. 2016-04-25 11:28:22 +03:00
Istvan Csomortani ad227c1af0 up_axi: Wait more to a valid read acknowledge. 2016-04-25 10:34:17 +03:00
Rejeesh Kutty e9b199959a library/adcfifo- constraints update 2016-04-20 15:57:25 -04:00
AndreiGrozav 679d471d75 Merge branch 'hdl_2016_r1' into dev
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
Adrian Costina d7d8b2cf1c axi_usb_fx3: Integrated actual GPIF II interface, with 2 address lines 2016-04-19 14:38:26 +03:00
Istvan Csomortani e855ef38f4 axi_dacfifo: Initial commit
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 11:28:33 +03:00
Istvan Csomortani 42cd05ab19 ad_mem_asym: Add support for more ratios.
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
2016-04-19 11:18:30 +03:00
AndreiGrozav 6fe41ebb08 axi_hdmi_tx: Upgrade hdmi clipping process
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
2016-04-12 22:01:07 +03:00
Istvan Csomortani 69d721526a util_dacfifo: Add constraints file 2016-04-12 13:21:50 +03:00
Istvan Csomortani 255b0ebd40 util_dacfifo: Add dac_xfer_out control
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
AndreiGrozav b31cdac6bd util_gmii_to_rgmii: Updated to 2015.4
The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1
2016-03-23 10:14:18 +02:00
Rejeesh Kutty 46eddd04be library: port updates on mmcm 2016-03-22 12:50:59 -04:00
Rejeesh Kutty de4da6726b axi_clkgen: port updates on mmcm 2016-03-22 12:50:59 -04:00
Rejeesh Kutty 74408881c6 axi_ad9122: optional clock out control 2016-03-22 12:50:59 -04:00
Rejeesh Kutty 65b2e51958 common/mmcm: add another clock 2016-03-22 12:50:59 -04:00
AndreiGrozav 769fecbe00 axi_i2s_adi: Fixed clock association 2016-03-21 20:18:45 +02:00
Istvan Csomortani 373481360b util_dacfifo: Add a bypass option to the FIFO 2016-03-21 14:14:43 +02:00
AndreiGrozav 6d277733d5 axi_spdif_rx: Fixed the clock association 2016-03-18 13:58:13 +02:00
AndreiGrozav 28990e362a axi_spdif_tx: Fixed the clock association 2016-03-18 13:31:06 +02:00
Istvan Csomortani 896c734792 Revert "foobar"
This reverts commit a3cb8cac45.
2016-03-18 13:23:02 +02:00
Istvan Csomortani a3cb8cac45 foobar 2016-03-18 11:51:13 +02:00
Istvan Csomortani 665bfbc991 axi_ad7616: Add M_AXIS_READY_ENABLE parameter
m_axis_ready can be driven by the DMA or can have a constant active state. By default is always one.
2016-03-15 18:38:55 +02:00
AndreiGrozav 9b2a106aa0 axi_jesd_gt: changed clock and reset naming to be consistent with the other projects 2016-03-15 11:20:31 +02:00
AndreiGrozav 06b7916303 axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred 2016-03-15 10:18:25 +02:00
AndreiGrozav ef05642e26 axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred 2016-03-15 10:14:05 +02:00
AndreiGrozav b3ed38107c axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred 2016-03-15 10:12:45 +02:00
Rejeesh Kutty 8ecf5edaf8 ad9122- pat modes 2016-03-14 11:14:29 -04:00
AndreiGrozav 31cc91d1b9 adi_ip: Updated to 2014.4.2
- automatically infer clocks, resets, axim_mm and axis interfaces
2016-03-14 15:14:18 +02:00
Adrian Costina 33b265a742 Makefile: Update Makefiles 2016-03-14 09:31:17 +02:00
Istvan Csomortani 573146aa96 axi_ad7616: Fix the data width of the AXI stream interface 2016-03-10 16:38:53 +02:00
Lars-Peter Clausen 287770a201 axi_dmac: Fix tlast generation on AXI stream master
For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-03-08 10:53:59 +01:00
Adrian Costina 2524f19ae0 Updated interfaces Makefile and Makefiles for the libraries that depend on it 2016-03-07 12:31:41 +02:00
Rejeesh Kutty 583ef82fd0 ad9361- cmos mode 2016-03-04 10:39:48 -05:00
Rejeesh Kutty 7a320a3d34 ad_lvds* - updates 2016-03-04 10:39:48 -05:00
Rejeesh Kutty 7d2939be92 ad9361- cmos mode initial commit 2016-03-04 10:39:48 -05:00
Adrian Costina 377461e0d4 Merge branch 'hdl_2015_r2' into dev 2016-02-19 14:15:27 +02:00
Rejeesh Kutty a8e9d72273 adc/dac - prefix parameters 2016-02-17 14:16:04 -05:00
Istvan Csomortani e1c5d6a8f7 axi_ad9684: Fix constraint file 2016-02-12 14:38:59 +02:00
Istvan Csomortani a747fad540 axi_ad9361: tx_valid must be controlled by the TDD controller 2016-02-12 14:33:34 +02:00
Istvan Csomortani e381d5170c util_tdd_sync: Update the synchronization interface
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
Adrian Costina 0d67af370f util_upack: Fixed problem when dac valid isn't continuous from the DAC
In cases when the dac_valid_ from the DAC is not continuous, in some situations
there were two dac_valid pulses sent to the DMA.
2016-02-04 13:03:46 +02:00
Dragos Bogdan 3d3d1098b4 axi_ad7616: Default DATA_WIDTH is 8 bits 2016-01-28 16:02:01 +02:00
Istvan Csomortani 122667259f ad7616_sdz: Update Make file 2016-01-28 14:48:44 +02:00
Istvan Csomortani fbb0d368bf axi_ad7616: Add support for parallel interface 2016-01-28 12:37:22 +02:00
Istvan Csomortani cd43ebd8bc axi_ad7616: The OP_MODE parameter is no longer required 2016-01-26 11:05:33 +02:00
Istvan Csomortani 2a17ce275c axi_ad7616: Control inputs are controlled through GPIO
The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
Istvan Csomortani 4b962e8d72 spi_engine: The width of the counters depend on the current DATA_WIDTH 2016-01-20 15:44:06 +02:00
Istvan Csomortani 4cc69c0cac axi_ad9684: Add Makefile 2016-01-19 18:32:11 +02:00
István Csomortáni c865dbf353 axi_ad9680: Fix channel instantiation 2016-01-19 12:49:45 +02:00
István Csomortáni df3eefdca1 axi_ad9434: Update constraint file 2016-01-19 12:43:05 +02:00
Istvan Csomortani d1e638349b ad_serdes_clk : The reference clock selection line should by tied to 1
Just the CLKIN1 is used in the MMCM.
2016-01-19 11:18:00 +02:00
Istvan Csomortani c6cfd1a2b6 axi_ad9684: Initial check in 2016-01-19 11:13:45 +02:00
István Csomortáni 4f2b999999 axi_ad9680: Q_OR_I_N is not used in this channel 2016-01-13 16:26:22 +02:00
István Csomortáni 838b558176 axi_ad9434: Fix adc_status
adc_status was not driven by anything. Should be driven by adc_status_m1.
2016-01-13 12:21:42 +02:00
István Csomortáni 2dcd9136aa axi_ad6676: Delete confusing comment 2016-01-13 10:20:18 +02:00
Istvan Csomortani c29dd8fad5 axi_ad7616: Fix Makefile 2015-12-21 19:39:58 +02:00
Istvan Csomortani 0b55325db9 axi_ad7616: Fix IP packaging script 2015-12-21 19:39:14 +02:00
Istvan Csomortani 17e7d1b86f ad7616: Add Makefiles 2015-12-21 17:09:42 +02:00
Istvan Csomortani 8ae9de8fba axi_ad7616: Update core
+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
2015-12-14 16:00:56 +02:00
Istvan Csomortani 4e57170384 spi_engine: Update SPI Engine frame work
+ data width and number of SDI lines are configurable
+ axi_spi_engine module can have two different type of memory map interface (S_AXI or UP)
2015-12-14 15:57:54 +02:00
Istvan Csomortani 29a0f27cd1 ad_edge_detect: Add a flop to output, reset is active high 2015-12-14 15:40:29 +02:00
Rejeesh Kutty 4c2d08a9be ad9152: altera syntax error 2015-12-11 12:49:00 -05:00
Rejeesh Kutty bc93910ee5 ad9152: qsys updates 2015-12-10 16:04:10 -05:00
Rejeesh Kutty ff1d98a0c7 ad9144: duplicate include 2015-12-10 16:02:35 -05:00
Rejeesh Kutty ce906989d5 ad9152: qsys ip 2015-12-10 09:46:31 -05:00
Istvan Csomortani 12c95b059d ad_tdd_control: Remove tdd_enable_synced control line
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
Adrian Costina 5cf45b2978 axi_clkgen: Added phase related parameters 2015-12-02 18:50:23 +02:00
Istvan Csomortani 36febf8591 Merge branch 'master' into dev
Conflicts:
	library/axi_ad9361/axi_ad9361_ip.tcl
	library/axi_dmac/Makefile
	library/axi_dmac/axi_dmac_constr.ttcl
	library/axi_dmac/axi_dmac_ip.tcl
	library/common/ad_tdd_control.v
	projects/daq2/common/daq2_bd.tcl
	projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
	projects/fmcomms2/zc706pr/system_project.tcl
	projects/fmcomms2/zc706pr/system_top.v
	projects/usdrx1/common/usdrx1_bd.tcl

This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
Adrian Costina 667e49fe41 library: Axi_clkgen, added register for controlling the source clock.
Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
2015-11-25 11:16:32 +02:00
Adrian Costina df58646925 util_adcfifo: Updated altera interface 2015-11-25 10:20:06 +02:00
Istvan Csomortani 593c486168 ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received 2015-11-24 15:15:53 +02:00
Istvan Csomortani c70be7391f ad_tdd_control: Avoid unnecessary reset on control lines
No need to reset for tdd_last_burst, it's value depends on the tdd_burst_counter.
2015-11-24 15:13:18 +02:00
Adrian Costina ee0617661e axi_ad9680: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:45:12 +02:00
Adrian Costina f51871c1e4 axi_ad9144: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:44:07 +02:00
Adrian Costina 76823f95fa axi_ad9250: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:39:55 +02:00
Adrian Costina 275ec3d3a8 axi_ad9361: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:21:08 +02:00
Adrian Costina 250f3c917b axi_ad9361: Removed old signals from the altera device interface module 2015-11-24 11:20:35 +02:00
Adrian Costina fb269f7a29 util_cpack: Updated altera interfaces
- DMA side, simplified naming
- ADC side, added FIFO conduit per channel
2015-11-24 11:18:18 +02:00
Adrian Costina e6de2ade78 util_upack: Updated altera interfaces
- DMA side, simplified naming
- DAC side, added FIFO conduit per channel
2015-11-24 11:17:02 +02:00
Adrian Costina c5ff1674c6 axi_dmac: Updated fifo interfaces for easier connectivity 2015-11-24 11:08:28 +02:00
Adrian Costina e5d2f5be06 util_upack: Cosmetic changes 2015-11-24 10:55:10 +02:00
Adrian Costina 985f2ca020 library: ad_rst, added comment so that the registers are not minimized away 2015-11-24 10:33:38 +02:00
Istvan Csomortani bdf9754971 util_tdd_sync: Sync signals output reg is a false path source 2015-11-17 09:42:05 +02:00
Istvan Csomortani 9ba8c059ce ad_tdd_sync: Fix reset value of the pulse_counter 2015-11-13 18:31:24 +02:00
Istvan Csomortani d6eae81bc1 axi_ad7616: Add the control module to the core, finish up SPI integration 2015-11-13 18:14:21 +02:00
Adrian Costina 3c27b3a4c5 ad_lvds_in: Add single ended option 2015-11-13 12:13:09 +02:00
Istvan Csomortani 952a491f59 axi_ad7616: Add spi engine to the core 2015-11-12 16:12:16 +02:00
Istvan Csomortani b17fec689e ad_tdd_control: An active sync pulse can NOT be a reset for the control lines
By reset the control lines (RF, VCO and DP) on an active sync pulse, can cause glitches on the ENABLE/TXNRX lines. The sync pulse resets just the TDD counter.
2015-11-11 11:13:33 +02:00
Istvan Csomortani fc0f4bc414 axi_ad9361: Delete the old sync generator from the core
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
Istvan Csomortani a290611c09 util_tdd_sync: Initial commit
A synchronization signal generator for AD9361 running on TDD mode.
If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 10:46:11 +02:00
Istvan Csomortani e4927887fd spi_engine_offload: Add sync_bits to the IP files list 2015-11-10 13:35:15 +02:00
Istvan Csomortani 229cd079b9 spi_engine: Fix to support multiple SDI lines 2015-11-10 13:34:29 +02:00
Istvan Csomortani 64d1948ea0 axi_ad7616: Initial commit 2015-11-10 13:32:56 +02:00
Adrian Costina 5cc97c78d3 Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries 2015-11-10 09:32:50 +02:00
Adrian Costina e7fd964874 axi_clkgen: Added a second input clock option 2015-11-06 17:55:29 +02:00
Rejeesh Kutty 839e76996f axi_gpreg: added constraints 2015-11-05 11:28:37 -05:00
Rejeesh Kutty 482b740229 axi_gpreg: add buffer enable 2015-11-05 11:28:35 -05:00
Rejeesh Kutty 66d4f8fd58 util_gtlb: output receive/transmit clocks 2015-11-05 11:28:34 -05:00
Rejeesh Kutty 28bfeb442c util_gtlb- syntax error fixes 2015-11-05 11:28:31 -05:00
Adrian Costina 6d28a92b5b util_adcfifo: Added altera initial constraints file 2015-11-04 13:34:52 +02:00
Adrian Costina e8b84b3662 axi_dmac: Updated axis destination / source ports for altera component 2015-11-04 13:33:41 +02:00
Adrian Costina de53a61902 util_adcfifo: Put a limit on the read/write address from memory so there is no overflow
Added altera component
2015-11-04 13:31:50 +02:00
Adrian Costina 6cfc13a9dd common: Allow for the memory to be also symetrical 2015-11-04 13:28:02 +02:00
Rejeesh Kutty ad1cef1441 axi_gpreg: compile fixes 2015-11-03 14:29:00 -05:00
Rejeesh Kutty c8019b69fd axi_gpreg- added 2015-11-03 14:28:59 -05:00
Rejeesh Kutty 88f247a1de util_gtlb: use gpio 2015-11-03 14:28:57 -05:00
Istvan Csomortani cf58110a98 Merge branch 'dev' into dev_ad7616 2015-11-03 14:07:48 +02:00
Lars-Peter Clausen acd9efc528 axi_hdmi_tx: Add parameter to configure the output clock polarity
In order to maximize the window where it is safe to capture data we ideally
want to launch data on the opposite edge to which it is captured. Since the
edge on which data is captured depends on the connected device add a
parameter that allows to configure the launching edge.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
Istvan Csomortani a147acd791 spi_engine: Add support for multiple SDI lines.
By changing the parameter called SDI_DATA_WIDTH the spi framework can support multiple SDI lines.
The supported number of SDI lines are: 1, 2, 3 and 4.
2015-11-02 18:42:55 +02:00
Rejeesh Kutty 88568c21e1 util_gtlb: updates for latest axi_jesd_gt 2015-10-30 18:47:36 -04:00
Rejeesh Kutty 2b6ae00a44 library: add mfifo 2015-10-27 14:52:02 -04:00
Rejeesh Kutty f1ed27105f library/common- reset fix 2015-10-23 14:32:35 -04:00
Adrian Costina 32b3cfd8b9 axi_usb_fx3: Initial commit of the core with interface stub 2015-10-23 13:27:00 +03:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Istvan Csomortani 6fb56079ee library/util_gtlb: Add Makefile 2015-10-16 13:58:01 +03:00
Istvan Csomortani 8ecdb4a4ca library/tdd_control: Add common registers to the register map and fix init value of a register
+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
Rejeesh Kutty 44568f1f64 util_jesd_gt: bad idea, it is needed for ipi 2015-10-15 11:13:08 -04:00
Rejeesh Kutty a6ff1b13fc util_jesd_gt- remove unused parameters 2015-10-15 10:46:07 -04:00
Istvan Csomortani c9a5057b93 library/prcfg : Split data bus to channels
Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
Adrian Costina a753d506c5 axi_mc_controller: Removed channels, as no data needs to be streamed to DMA 2015-10-09 13:54:03 +03:00
Adrian Costina 694dbd3259 axi_mc_controller: Updated constraints 2015-10-09 13:53:13 +03:00
Adrian Costina 7c3646e863 axi_mc_current_monitor: Removed stub channel 2015-10-09 13:52:14 +03:00
Adrian Costina 99e6240126 axi_mc_current_monitor: Updated constraints 2015-10-09 13:51:15 +03:00
Adrian Costina d19d9c8fbc axi_mc_speed: Corrected maximum number of channels 2015-10-09 13:50:25 +03:00
Adrian Costina ce01185348 axi_mc_speed: Updated constraints 2015-10-09 13:50:08 +03:00
Adrian Costina 96d363849e ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block 2015-10-09 13:43:14 +03:00
Adrian Costina df8ac2e726 axi_ad9671: Updated constraints 2015-10-09 13:15:55 +03:00
Adrian Costina 03b225a802 axi_ad9671: Fixed synchronization mechanism 2015-10-09 13:15:12 +03:00
Istvan Csomortani 8321d5a4fb util_dacfifo: Update read out method
Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
2015-10-08 17:13:12 +03:00
Istvan Csomortani 1ebd38c514 util_dacfifo: Update read out method
Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
2015-10-08 16:50:36 +03:00
Rejeesh Kutty cd9754afbe up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty f3ffd5a63f up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty 2b894bc13e up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty 5c3f90a676 up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty ba70c7a4ea ad9144- ip updates 2015-09-30 11:37:10 -04:00
Rejeesh Kutty 54fcf06eed ad9152- ip updates 2015-09-30 11:34:09 -04:00
Istvan Csomortani 81a1c21553 util_pmod_adc: Reset line changed to active low reset. 2015-09-30 12:33:46 +03:00
Istvan Csomortani 97a9ecfc9a axi_hdmi_rx: Update constraint file and fix reset line 2015-09-29 18:49:30 +03:00
Istvan Csomortani b765be568f up_gt_channel: Delete the register, which stores transceiver type
Transceiver type is stored in axi_jesd_gt/up_gt only.
2015-09-29 14:23:42 +03:00
Istvan Csomortani cffb2e6226 up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address 2015-09-29 14:19:52 +03:00
Istvan Csomortani a0ac0e912b up/ad_gt_common/channel: Cosmetic changes 2015-09-29 14:16:24 +03:00
Adrian Costina dff6c0df01 axi_ad9652: Updated with the latest constraints 2015-09-28 11:29:07 +03:00
Istvan Csomortani c03983ca54 ad_tdd_sync/control: Update TDD logic
+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
2015-09-25 19:11:23 +03:00
Istvan Csomortani 07e2d281c0 Make: Update Make files 2015-09-25 19:11:21 +03:00
Istvan Csomortani 884973fdbb util_dacfifo: Cosmetic changes 2015-09-25 17:41:44 +03:00
Adrian Costina 2816812e0a axi_ad9625: Updated constraints and added adc reset port 2015-09-25 17:16:31 +03:00
Adrian Costina 37a4e976d6 axi_ad6676: Updated constraints 2015-09-25 17:02:42 +03:00
Adrian Costina 061f468fb1 axi_ad9250: Update library
- added adc reset port
- addded common constraints
2015-09-24 19:10:19 +03:00
Istvan Csomortani ebaebc54f7 axi_ad9680: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:29 +03:00
Istvan Csomortani 9ad59c58db axi_ad9234: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:18 +03:00
Istvan Csomortani 0b08250261 axi_ad9152: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:08 +03:00
Istvan Csomortani 892755c084 axi_ad9144: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:18:48 +03:00
Istvan Csomortani 5e082be963 axi_ad9680: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:14:01 +03:00
Istvan Csomortani edb94ada8b axi_ad9234: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:13:20 +03:00
Istvan Csomortani d45f49c062 axi_ad9152: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:12:36 +03:00
Istvan Csomortani 0a4f43efea axi_ad9144: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:11:29 +03:00
Istvan Csomortani 900db3d8ed util_wfifo: Fix reset related timing violation
The memory instance reset connected to ground, rather than connect to dout_rstn.
2015-09-23 16:36:33 +03:00
Istvan Csomortani 516c59523d util_wfifo: Cosmetic changes. 2015-09-23 16:36:31 +03:00
Istvan Csomortani 568333bbfc axi_dmac: Fix typo on ./bd/bd.tcl 2015-09-23 15:51:50 +03:00
Istvan Csomortani aa608e3907 axi_ad9467: Update constraints 2015-09-23 14:26:57 +03:00
Istvan Csomortani 0411ad2386 axi_ad9434: Update constraints 2015-09-23 14:26:55 +03:00
Istvan Csomortani ab8256cf92 ad_tdd_control: Redesign the state machine to prevent timing failure. 2015-09-22 10:33:50 +03:00
Lars-Peter Clausen cd93beb10f util_axis_fifo: Remove m_axis_addr_next output from the address modules
Remove m_axis_addr_next output from the address modules since it is no
longer used.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
Lars-Peter Clausen 5c22e622de axi_dmac: Fix width for dest response FIFO
The width of the dest response FIFO is 1 bit not 3 bits.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
Lars-Peter Clausen cfd57fc462 axi_dmac: Drive unused interface output ports with const value
Drive all output pins of the disabled interfaces with a constant value.
This avoids warnings from the tools about not driven output ports.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
Lars-Peter Clausen fed14cf613 axi_dmac: Mark unused output ports explicitly as unconnected
Mark all unused output ports explicitly as explicitly. This makes it clear
that they are left unconnected on purpose and avoids warnings from the
tools about unconnected ports.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
Lars-Peter Clausen a7f4b11624 axi_dmac: Beautify IPI GUI
Group the axi_dmac parameters by function and provide a human readable name
for the IPI GUI. This makes it easier to understand what parameter does
what when using the IPI GUI to configure the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
Lars-Peter Clausen 5b5a4707d2 axi_dmac: Add validation values to IPI package
Add validation values for the different configuration parameters. This
enables the tools to check whether the configured value is valid and avoids
accidental misconfiguration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
Lars-Peter Clausen 104e49d515 axi_dmac: Remove unused address bits on AXI-Lite bus
The address width for the AXI-Lite configuration bus for the core is only
14 bit. Remove the upper unused bits from the public interface.

This allows infrastructure code to know about this and it might be able to
perform optimizations of the interconnect based on this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
Lars-Peter Clausen 89ceae3757 axi_dmac: Move m_axi_src interface clock and reset next to other signals
Move the clock and reset signals of the m_axi_src interface next to the
other signals in the module definition.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:24 +02:00
Lars-Peter Clausen 5aa11feb48 axi_dmac: Change BRAM REGCEB constraint to set_false_path
According to the documentation when using a BRAM block in SDP mode the
REGCEB pin is not used and should be connected to GND. The tools though
when inferring a BRAM connect REGCEB to the same signal REGCEA. This causes
issues with timing verification since the REGCEB pin is associated with the
write clock whereas the REGCEA pin is associated with the read clock.

Until this is fixed in the tools mark all paths to the REGCEB pin as false
paths.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:22 +02:00
Lars-Peter Clausen 4c51224696 axi_dmac: Configure AXI master bus properties according to core configuration
Configure the maximum burst size as well as the maximum number of active
requests on the AXI master interfaces according to the core configuration.
This allows connected slaves to know what kind of requests to expect and
allows them to configure themselves accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:19 +02:00
Lars-Peter Clausen 12fc6d1672 axi_dmac: Indicate that the core does not issue narrow AXI bursts
The axi_dmac core does not issue narrow AXI bursts. Indicate this by
setting the SUPPORTS_NARROW_BURST property to 0 on both AXI master
interfaces.

This allows connected slaves to know that they will not receive narrow
bursts, which allows them to disable support for it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:18 +02:00
Lars-Peter Clausen 5f307f862f axi_dmac: Use sane defaults for the AXI protocol type
The axi_dmac core generates requests which are both AXI3 and AXI4
compliant. This means it is possible to connect it to both a AXI3 or AXI4
slave port without needing a AXI protocol converter.  Unfortunately it is
not possible to declare a port as both AXI3 and AXI4 compliant, so the core
has the C_DMA_AXI_PROTCOL_SRC and C_DMA_AXI_PROTOCOL_DEST parameters, which
allow to configure the protocol type of the corresponding AXI master
interface. Currently the default is always AXI4.

But when being used on ZYNQ it is most likely that the AXI master interface
of the DMAC core ends up being connected to the AXI3, so change the default
to AXI3 if the core is instantiated in a ZYNQ design.

The default can still be overwritten by explicitly setting the
configuration property.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:17 +02:00
Lars-Peter Clausen f079b2193a axi_dmac: Add support for auto-detecting asynchronous clock configuration
Add support for querying the clock domains of the clock pins for the
axi_dmac controller. This allows the core to automatically figure out
whether its different parts run in different clock domains or not and setup
the configuration parameters accordingly.

Being able to auto-detect those configuration parameters makes the core
easier to use and also avoids accidental misconfiguration.

It is still possible to automatically overwrite the configuration
parameters by hand if necessary.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:15 +02:00
Lars-Peter Clausen 19f7d8500c adi_ip.tcl: Add support for adding bd files to a core
bd files can be used to automate certain tasks in IP integrator when the
core is instantiated. Add a helper command for adding such files to a core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:14 +02:00
Lars-Peter Clausen 39320ef48b axi_dmac: Fix source pause signal
For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:13 +02:00
Lars-Peter Clausen 91bb54467b axi_dmac: Generate per core instance constraint file
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.

This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.

This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:12 +02:00
Lars-Peter Clausen 0f5f21eec2 adi_ip.tcl: Add helper function to add TTCL files to a core
Add a helper function which allows to add TTCL templates files to a core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:10 +02:00
Adrian Costina 46808c4c41 util_wfifo: Changed some reset for several registers from asynchronous to synchronous for better integration with the FIFO 2015-09-16 18:55:47 +03:00
Adrian Costina 6804f3377a axi_ad9643: Updated core with latest constraints 2015-09-16 15:49:13 +03:00
Adrian Costina 5347c058df axi_ad9122: Updated core with latest constraints 2015-09-16 15:48:33 +03:00
Adrian Costina 884f45c81d common library: Registered dc_filter and iq_correction coefficients 2015-09-16 14:24:18 +03:00
Lars-Peter Clausen 052860cbc3 axi_dmac: Fix source pause signal
For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-16 11:02:08 +02:00
Lars-Peter Clausen 5af371db6b axi_dmac: Generate per core instance constraint file
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.

This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.

This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-15 19:54:33 +02:00
Lars-Peter Clausen 522f30ce21 adi_ip.tcl: Add helper function to add TTCL files to a core
Add a helper function which allows to add TTCL templates files to a core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-15 19:00:56 +02:00
Adrian Costina 7c896ba5f8 axi_ad9361: Fixed constraints definition 2015-09-14 18:20:30 +03:00
Adrian Costina 67ffeb18e8 axi_ad9739a: Updated core with latest constraints 2015-09-11 14:04:33 +03:00
Adrian Costina e33403816c axi_ad9265: Updated core with latest constraints 2015-09-11 11:26:28 +03:00
Istvan Csomortani 5bc16159fa ad_tdd_sync: The resync will reset all the control lines 2015-09-10 11:28:36 +03:00
Istvan Csomortani a679251d7d Makefiles: Update Make 2015-09-09 17:13:19 +03:00
Istvan Csomortani 85ffc25ec5 ad_tdd_sync: Update the synchronization logic
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
Istvan Csomortani 5a566b9e5d ad_tdd_control: Add delay compensation for the control lines 2015-09-09 12:24:26 +03:00
Istvan Csomortani 6acb350ee5 axi_dmac: Update for axi_dmac_constr.xdc
Parameter called 'processing_order' default value is 'late'. No need to specify it at process call.
2015-09-09 12:08:35 +03:00
Rejeesh Kutty 381ffd43c1 gtlb- remove pn test-reset 2015-09-08 13:52:33 -04:00
Rejeesh Kutty 9bef9742b7 jesd_gt- cosmetic changes 2015-09-03 16:16:24 -04:00
Rejeesh Kutty 84ced344d9 gtlb- up-sync make w1c 2015-09-03 16:16:22 -04:00
Lars-Peter Clausen e0b5044aa3 axi_dmac: Disable dummy AXI ports for Xilinx IPI
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.

The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
Rejeesh Kutty 2a09257f38 pzslb- updates - wip 2015-08-31 15:41:28 -04:00
Rejeesh Kutty c1b01517f8 util_gtlb: added 2015-08-31 15:41:22 -04:00
Rejeesh Kutty 1e5afdd535 axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 6cf7eb5ad4 axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 4554eb03b0 axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 704385a8dc axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty a33c08725b axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 1cd3435147 up_delay_cntrl- cosmetics 2015-08-28 13:16:18 -04:00
Rejeesh Kutty 8fddf983d2 up_hdmi_tx- common/generic instance names 2015-08-27 13:17:06 -04:00
Rejeesh Kutty 88f806f584 ad9361- alt io matching 2015-08-27 11:55:24 -04:00
Rejeesh Kutty 74e72021f7 ad9361- ensm through dev-if 2015-08-27 11:41:53 -04:00
Rejeesh Kutty 664ef017bb ad9361- ensm through dev-if 2015-08-27 11:41:52 -04:00
Rejeesh Kutty 29b0ec0378 ad9361- ensm through dev-if 2015-08-27 11:41:51 -04:00
Rejeesh Kutty d82d37c23f ad9361- ensm through dev-if 2015-08-27 11:41:49 -04:00
Rejeesh Kutty 2259b6cbf7 ad9361- ensm through dev-if 2015-08-27 11:41:48 -04:00
Rejeesh Kutty 20ee10ea46 common/ad_lvds_out- add single ended 2015-08-27 11:41:47 -04:00
Rejeesh Kutty c56b534ec0 dacfifo- remove interfaces 2015-08-27 11:18:00 -04:00
Rejeesh Kutty ba64de228e ip-constr- register name changes 2015-08-27 11:18:00 -04:00
Rejeesh Kutty f3410a7db1 xpack- remove useless interfaces 2015-08-26 14:12:14 -04:00
Rejeesh Kutty b0d22d323a ad9361- axi-clock definitions 2015-08-26 14:11:43 -04:00
Rejeesh Kutty 4655af7bf6 2015.2 updates 2015-08-26 11:33:44 -04:00
Rejeesh Kutty 18f688514b 2015.2 updates 2015-08-26 11:33:37 -04:00
Rejeesh Kutty 7780b3a3a2 2015.2 updates 2015-08-26 11:33:27 -04:00
Istvan Csomortani 7b858bc5ad Revert commit 6b99ce
Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
Istvan Csomortani 386cc74ab4 util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl
Fix port names at the 'port_maps' attribute of the adi_add_bus process call.
2015-08-25 09:41:34 +03:00
Istvan Csomortani c2ea667a01 library/IPI: Set ASSOCIATED_RESET parameter for AXI interface
For some reason, if a core has an AXI and an AXI Stream interface too, the tool sets the AXI interface's ASSOCIATED_RESET parameter to the AXI Stream interface's reset.
This cause an unconnected AXI reset port in the block design. This 'set_property' command intended to overwrite this automated setup.
2015-08-25 09:36:42 +03:00
Istvan Csomortani 0c3f110bff library: Fix broken parameters
Fix the broken parameters for the following IP cores: axi_i2s_adi, axi_spdif_tx, util_cpack. Make additional name changes on the local parameters.
2015-08-25 09:19:47 +03:00
Istvan Csomortani da315eb6c0 library: 2015.2 updates
IPI bus interface names have changed in this new release.
2015-08-25 09:13:24 +03:00
Rejeesh Kutty 0077117f94 dac/adc- make common instances 2015-08-21 14:41:39 -04:00
Rejeesh Kutty c45d39df51 dac/adc- make common instances 2015-08-21 14:41:35 -04:00
Rejeesh Kutty e3ec6b48fc dac/adc- make common instances 2015-08-21 14:41:30 -04:00
Rejeesh Kutty f31c1c9caa dac/adc- make common instances 2015-08-21 14:41:26 -04:00
Rejeesh Kutty e4e4700950 dac/adc- make common instances 2015-08-21 14:41:13 -04:00
Rejeesh Kutty 54b4365f6c dac/adc- make common instances 2015-08-21 14:41:09 -04:00
Rejeesh Kutty 799001403f mult-macro: use primitive parameters 2015-08-20 13:54:16 -04:00
Rejeesh Kutty 111287604b xcvr- remove status constraint 2015-08-20 13:54:15 -04:00
Lars-Peter Clausen 0d482e7ef6 axi_dmac: Disable dummy AXI ports for Xilinx IPI
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.

The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 18:25:01 +02:00
Lars-Peter Clausen 37c14e782d axi_dmac: Disable dummy AXI ports for Xilinx IPI
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.

The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 18:12:10 +02:00
Rejeesh Kutty d59ec3b36d unused ip cores 2015-08-20 11:37:16 -04:00
Rejeesh Kutty b0079e60bf ad-rst - common instance for adc/dac 2015-08-20 11:37:16 -04:00
Adrian Costina d67a4a3088 axi_ad9434: Removed duplicate parameter 2015-08-20 18:19:59 +03:00
Adrian Costina 6b99ce2482 library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2 2015-08-20 18:17:38 +03:00
Adrian Costina 6ae0c8f85e library: Fixed changes related to parameters 2015-08-20 18:13:54 +03:00
Istvan Csomortani 0d1d8310fd axi_dmac: Parameter changes
Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 16:06:26 +03:00
Rejeesh Kutty 82e703df23 parameter changes 2015-08-20 08:53:51 -04:00
Istvan Csomortani db18924f8a library/scripts: Fix ipx::get_file_groups process call
ipx::get_file_groups does not work, if there is specified just a [<pattern>] for its argument. Need to use a -filter to get proper result.
2015-08-20 10:56:37 +03:00
Istvan Csomortani 0dfb3e2019 tcl_scripts: Update Vivado version number to 2015.2.1 2015-08-20 10:50:52 +03:00
Istvan Csomortani d52308f074 axi_dmac: Change parameter name 2D_TRANSFER
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
Rejeesh Kutty 6ab28ccb0c axi-jesd-xcvr- parameter changes 2015-08-19 14:55:11 -04:00
Rejeesh Kutty 28eb09b4d5 axi-jesd-xcvr- parameter changes 2015-08-19 14:55:08 -04:00
Rejeesh Kutty 928ee4972b dac/adc-rst: common ad-rst instance 2015-08-19 14:54:43 -04:00
Rejeesh Kutty 483e375910 dac/adc-rst: common ad-rst instance 2015-08-19 14:54:38 -04:00
Rejeesh Kutty 5e252f17b9 cpack- ad_rst port addition 2015-08-19 13:26:38 -04:00
Rejeesh Kutty f8b3346e97 axi_jesd_xcvr- ad_rst register changes 2015-08-19 13:26:38 -04:00
Rejeesh Kutty f7f902c7b4 axi_jesd_xcvr- ad_rst register changes 2015-08-19 13:26:38 -04:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
Istvan Csomortani 549801cf2e library: Delete unused IP cores
Delete IP "controllerperipheralhdladi_pcore" and "ip_pid_controller"
2015-08-19 12:24:10 +03:00
Istvan Csomortani 10d9de39a1 axi_ad9361/tdd: Update the synchronization logic
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
Istvan Csomortani bcee3e04d4 fmcomms2_tdd: Update tdd_enabaled path
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
Istvan Csomortani 8e536ad8d1 axi_ad9361: Update Make file 2015-08-19 12:14:03 +03:00
Paul Cercueil e64baad54a axi_dmac: Fix a bug occuring on transfers < one beat
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2015-08-19 10:23:26 +02:00
Paul Cercueil 114d48d4e1 axi_dmac: Fix a bug occuring on transfers < one beat
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2015-08-19 10:23:06 +02:00
Adrian Costina f5de5ca487 usdrx1: Fixed jesd core parameters. Fixed synchronization mechanism 2015-08-19 10:12:24 +03:00
Istvan Csomortani b84afcdcd1 Merge branch 'master' into dev
Conflicts:
	library/Makefile
	library/axi_ad6676/axi_ad6676_ip.tcl
	library/axi_ad9122/axi_ad9122_core.v
	library/axi_ad9122/axi_ad9122_ip.tcl
	library/axi_ad9144/axi_ad9144_ip.tcl
	library/axi_ad9152/axi_ad9152_ip.tcl
	library/axi_ad9234/axi_ad9234_ip.tcl
	library/axi_ad9250/axi_ad9250_hw.tcl
	library/axi_ad9250/axi_ad9250_ip.tcl
	library/axi_ad9361/axi_ad9361.v
	library/axi_ad9361/axi_ad9361_dev_if_alt.v
	library/axi_ad9361/axi_ad9361_ip.tcl
	library/axi_ad9361/axi_ad9361_rx_channel.v
	library/axi_ad9361/axi_ad9361_tdd.v
	library/axi_ad9361/axi_ad9361_tx_channel.v
	library/axi_ad9625/axi_ad9625_ip.tcl
	library/axi_ad9643/axi_ad9643_channel.v
	library/axi_ad9643/axi_ad9643_ip.tcl
	library/axi_ad9652/axi_ad9652_channel.v
	library/axi_ad9652/axi_ad9652_ip.tcl
	library/axi_ad9671/axi_ad9671_constr.xdc
	library/axi_ad9671/axi_ad9671_ip.tcl
	library/axi_ad9680/axi_ad9680_ip.tcl
	library/axi_ad9739a/axi_ad9739a_ip.tcl
	library/axi_dmac/axi_dmac_constr.sdc
	library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
	library/axi_jesd_gt/axi_jesd_gt_constr.xdc
	library/axi_jesd_gt/axi_jesd_gt_ip.tcl
	library/axi_mc_speed/axi_mc_speed_constr.xdc
	library/common/ad_gt_channel_1.v
	library/common/ad_gt_common_1.v
	library/common/ad_gt_es.v
	library/common/ad_iqcor.v
	library/common/ad_jesd_align.v
	library/common/ad_rst.v
	library/common/altera/ad_xcvr_rx_rst.v
	library/common/up_adc_common.v
	library/common/up_axis_dma_rx.v
	library/common/up_axis_dma_tx.v
	library/common/up_clkgen.v
	library/common/up_clock_mon.v
	library/common/up_dac_common.v
	library/common/up_gt.v
	library/common/up_hdmi_tx.v
	library/common/up_tdd_cntrl.v
	library/common/up_xfer_cntrl.v
	library/common/up_xfer_status.v
	library/util_cpack/util_cpack.v
	library/util_cpack/util_cpack_ip.tcl
	library/util_dac_unpack/util_dac_unpack_hw.tcl
	library/util_jesd_align/util_jesd_align.v
	library/util_jesd_xmit/util_jesd_xmit.v
	library/util_upack/util_upack_ip.tcl
	library/util_wfifo/util_wfifo.v
	library/util_wfifo/util_wfifo_constr.xdc
	library/util_wfifo/util_wfifo_ip.tcl
	projects/arradio/c5soc/system_bd.qsys
	projects/common/vc707/vc707_system_bd.tcl
	projects/common/zc706/zc706_system_plddr3.tcl
	projects/daq2/a10gx/Makefile
	projects/daq2/a10gx/system_bd.qsys
	projects/daq3/common/daq3_bd.tcl
	projects/daq3/zc706/system_bd.tcl
	projects/fmcjesdadc1/a5gt/Makefile
	projects/fmcjesdadc1/a5gt/system_bd.qsys
	projects/fmcjesdadc1/a5gt/system_constr.sdc
	projects/fmcjesdadc1/a5gt/system_top.v
	projects/fmcjesdadc1/a5soc/system_bd.qsys
	projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
	projects/fmcomms1/ac701/system_bd.tcl
	projects/fmcomms1/common/fmcomms1_bd.tcl
	projects/fmcomms1/kc705/system_bd.tcl
	projects/fmcomms1/vc707/system_bd.tcl
	projects/fmcomms1/zc702/system_bd.tcl
	projects/fmcomms1/zc702/system_top.v
	projects/fmcomms1/zc706/system_bd.tcl
	projects/fmcomms1/zc706/system_top.v
	projects/fmcomms1/zed/system_bd.tcl
	projects/fmcomms1/zed/system_top.v
	projects/fmcomms2/ac701/system_constr.xdc
	projects/fmcomms2/common/fmcomms2_bd.tcl
	projects/fmcomms2/kc705/system_constr.xdc
	projects/fmcomms2/kc705/system_top.v
	projects/fmcomms2/mitx045/system_top.v
	projects/fmcomms2/rfsom/system_constr.xdc
	projects/fmcomms2/rfsom/system_top.v
	projects/fmcomms2/vc707/system_top.v
	projects/fmcomms2/zc706/system_bd.tcl
	projects/fmcomms2/zc706/system_constr.xdc
	projects/fmcomms2/zc706/system_top.v
	projects/fmcomms2/zed/system_top.v
	projects/imageon/zc706/system_constr.xdc
	projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
	projects/motcon2_fmc/zed/system_constr.xdc
	projects/motcon2_fmc/zed/system_top.v
	projects/usdrx1/a5gt/Makefile
	projects/usdrx1/a5gt/system_bd.qsys
	projects/usdrx1/common/usdrx1_bd.tcl

Conflicts were resolved using 'Mine' (/dev).
2015-08-17 15:15:58 +03:00
Rejeesh Kutty c22d1c044b axi_jesd_gt-- gt interfaces 2015-08-14 15:34:49 -04:00
Rejeesh Kutty 890f743f1a util_jesd_gt-- gt interfaces 2015-08-14 15:34:30 -04:00
Rejeesh Kutty 6eb0b5eeda scripts-- add interface procedures 2015-08-14 15:33:58 -04:00
Rejeesh Kutty 2345be2237 interfaces-- transceiver cores 2015-08-14 15:33:36 -04:00
Rejeesh Kutty af87b65788 interfaces_ip: added 2015-08-14 11:24:27 -04:00
Rejeesh Kutty ebecfde64c axi_hdmi_tx: common constraints & async resets 2015-08-13 13:03:51 -04:00
Rejeesh Kutty a6f6c81795 axi_jesd_gt- gt lane split 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 041be729f6 common/ip-constrs- uniform simple constraints will do 2015-08-13 13:03:51 -04:00
Rejeesh Kutty a2b816beda common/up_hdmi_tx: wrong clock on vdma status signals 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 5edf61c40a ad_rst:- allow preset to be synchronized as reset 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 2bcac36e33 common/up_- change to asynchronous resets 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 2b8e1bdb74 adi_ip- parse file list for constraints 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 3615c9cad7 axi_jesd_gt- bug fixes 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 44d51e665d util_jesd_gt- port type fix 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 8697b0a8d6 axi_jesd_gt- ip script changes 2015-08-13 13:03:51 -04:00
Rejeesh Kutty e265ca9ea7 util_jesd_gt- ip tcl changes 2015-08-13 13:03:51 -04:00
Rejeesh Kutty a108ca9309 util_jesd_gt- updates 2015-08-13 13:03:51 -04:00
Rejeesh Kutty a4076424e0 util_jesd_gt- added 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 10d4da64dd axi_jesd_gt: move master/slave control to a util module 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 3ed350efbc axi_jesd_gt- split up 2015-08-13 13:03:51 -04:00
Rejeesh Kutty e4f94664a6 axi_jesd_gt- remove per lane control/status to channel 2015-08-13 13:03:51 -04:00
Rejeesh Kutty f807490ed1 axi_jesd_gt- per lane group 2015-08-13 13:03:51 -04:00
Rejeesh Kutty 4c8206608c axi_jesd_gt- separate es-axi 2015-08-13 13:03:51 -04:00
Rejeesh Kutty e4b0710923 axi_jesd_gt- per lane split-up 2015-08-13 13:03:51 -04:00
Adrian Costina ce26373e8a axi_ad9671: updated constraints to apply in all cases 2015-08-13 11:53:15 +03:00
Adrian Costina 0379279bd4 axi_ad9671: Fixed rx_sof pin name 2015-08-12 10:20:09 +03:00
Adrian Costina afb9911b6e Makefiles: Updated makefiles 2015-08-06 19:50:50 +03:00
Istvan Csomortani f59058dd8a axi_ad9434: Fix the up interface for IO_DELAYs 2015-08-06 15:17:19 +03:00
Istvan Csomortani ad80561379 TDD_regmap: Fix CDC for control signals 2015-08-06 15:16:39 +03:00
Istvan Csomortani e19d476b58 TDD_regmap: Fix addresses 2015-08-06 15:15:50 +03:00
Istvan Csomortani d2c99acae8 fmcomms2/TDD: Update synchronization interface
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
Istvan Csomortani 6104061d19 axi_ad9434: Fix the up interface for IO_DELAYs 2015-08-04 13:46:15 +03:00
Istvan Csomortani cfc4046821 fmcomms2: Add a synchronization interface for TDD mode.
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write  0x01 into TDD register 0x50.
2015-07-29 14:10:56 +03:00
Istvan Csomortani ed6bdf66bd axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-29 11:59:17 +03:00
Istvan Csomortani 05ba125694 ad_tdd_control: Connect the reset to all the flops 2015-07-29 11:56:40 +03:00
Istvan Csomortani 8e631e56d6 fmcomms2: Add a synchronization interface for TDD mode.
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write  0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
Adrian Costina d5d7a24483 util_cpack: Added reset interface 2015-07-28 11:00:54 +03:00
Adrian Costina 623c3dc333 axi_ad9361: Updated altera core by including tdd related files. Removed deleted ports 2015-07-24 16:41:41 +03:00
Rejeesh Kutty caca364c61 ad9652- iqcor iqsel changes 2015-07-24 08:35:13 -04:00
Rejeesh Kutty 144b8f7383 ad9643- iqcor iqsel changes 2015-07-24 08:34:52 -04:00
Adrian Costina 43946a54a4 axi_dmac: Added C_FIFO_SIZE parameter 2015-07-24 15:30:10 +03:00
Rejeesh Kutty 649297a0e3 ad_iqcor- changes 2015-07-23 16:20:46 -04:00
Rejeesh Kutty cd5ce3349f iqcor- move i/q sel inside the module 2015-07-23 15:55:45 -04:00
Adrian Costina 3d1ffe7bd2 util_cpack: Added reset interface 2015-07-23 17:01:53 +03:00
Adrian Costina f7d28e0944 axi_dmac: Removed unneded constraints, as FMCJESDADC1 doesn't work correctly with them 2015-07-23 17:01:02 +03:00
Adrian Costina 41e9a34886 axi_ad9250: Changed Altera interface specification to be compatible with upack 2015-07-23 16:59:57 +03:00
Rejeesh Kutty 901bcb2c06 dma- constraints modifications 2015-07-22 12:46:06 -04:00
Rejeesh Kutty 3d7afb8fc5 jesd-xcvr: constraints modifications 2015-07-22 12:46:06 -04:00
Rejeesh Kutty 6352884398 jesd-xcvr: common align function 2015-07-22 12:46:06 -04:00
Rejeesh Kutty a4461545fa axi-ip: constraints - altera 2015-07-22 12:46:06 -04:00
Istvan Csomortani ac39329046 axi_spdif_rx: Fix the pl330_dma control path
- fix pl330_dma control path
- delete unused control_reg bits
- change the port name spdif_rx_i_osc to spdif_rx_i_dbg
- version_reg is read only
2015-07-22 17:59:52 +03:00
Rejeesh Kutty 559893c0a3 altera- obsolete cores 2015-07-21 11:04:26 -04:00
Rejeesh Kutty 86dabbe5fc jesd-align-- xilinx/altera merge 2015-07-21 10:57:00 -04:00
Rejeesh Kutty 3a4581a8df axi-xcvr: removed xcvr compoents 2015-07-21 10:56:04 -04:00
Rejeesh Kutty 264f9ffbfc ip_alt- avalon/reset definitions 2015-07-21 10:55:13 -04:00
Rejeesh Kutty 3101045109 qsys- library group 2015-07-17 10:07:15 -04:00
Rejeesh Kutty 4e99a2cb01 xcvr: remove signal tap 2015-07-16 08:09:56 -04:00
Istvan Csomortani 9f7fff2d2f axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
Rejeesh Kutty 31584cf27e ad9680- qsys needs interface signal name matching 2015-07-15 15:59:51 -04:00
Rejeesh Kutty 60c344cea6 ad9144- qsys needs interface signal name matching 2015-07-15 15:59:51 -04:00
Rejeesh Kutty 29c6e90d38 util_bsplit: remove avalon streaming interface 2015-07-15 09:44:57 -04:00
Rejeesh Kutty af898de818 axi_jesd_xcvr: remove avalon streaming interface 2015-07-15 09:44:56 -04:00
Rejeesh Kutty ea57e49da7 axi_ad9250: remove avalon streaming interface 2015-07-15 09:44:54 -04:00
Rejeesh Kutty 6e3817d419 axi_jesd_xcvr: individual reset control 2015-07-13 10:04:34 -04:00
Rejeesh Kutty 8d6c39d307 ad9680- remove avalon streaming 2015-07-13 10:03:38 -04:00
Rejeesh Kutty c69e36314c ad9144- remove avalon streaming 2015-07-13 10:03:16 -04:00
Rejeesh Kutty 9d95ddc620 reset and clock additions 2015-07-09 14:29:08 -04:00
Rejeesh Kutty d6d263341e signal tap needs another method 2015-07-08 15:47:47 -04:00
Rejeesh Kutty b25b2e3020 registers for signal tap 2015-07-08 15:47:45 -04:00
Adrian Costina c972779217 motcon2_fmc: updated util_gmii_to_rgmii and motcon2_fmc project for improved performance of the ethernet
- removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core
- removed delay related xdc constraints as they are not needed
2015-07-08 16:23:33 +03:00
Adrian Costina b4eb7465ed library: Add missing Makefiles for axi_spdif_rx, util_jesd_align, util_jesd_xmit 2015-07-08 10:48:58 +03:00
Rejeesh Kutty 23428ac48b transceiver constraints for sysref 2015-07-07 15:25:36 -04:00
Rejeesh Kutty ea2bd71904 synchronize up signals separately 2015-07-07 12:51:13 -04:00
Rejeesh Kutty c1fcbeec8e library/axi_jesd_xcvr: interface name matching 2015-07-07 10:21:53 -04:00
Rejeesh Kutty b106b8a8f4 library/axi_jesd_xcvr: updates 2015-07-06 13:51:55 -04:00
Rejeesh Kutty c67ca682a4 hw.tcl- added 2015-07-06 13:51:55 -04:00
Rejeesh Kutty 1cfe6fe792 axi_jesd_xcvr: initial commit 2015-07-06 13:51:55 -04:00
Rejeesh Kutty 3a5da47239 xcvr- initial checkin 2015-07-06 13:51:55 -04:00
Istvan Csomortani 46fa91d5be Makefile: Update Make files 2015-07-03 18:08:57 +03:00
Istvan Csomortani 7376218e01 axi_spdif_rx: Initial commit
NOT tested.
2015-07-03 17:46:45 +03:00
Adrian Costina 896888d495 axi_mc_current_monitor: updated ad7401 driver to send unsigned data 2015-07-02 14:23:19 +03:00
Adrian Costina 04527f8b18 axi_mc_current_monitor: updated ad7401 driver to send unsigned data 2015-07-02 14:21:26 +03:00
Lars-Peter Clausen 3c6d19d33d axi_hdmi_tx_es: Drop strange port initializers
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen 26b0ff9853 axi_hdmi_tx: Don't accidentally send control characters in embedded sync mode
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen 6aee17da83 axi_hdmi_tx: Add control to bypass chroma sub-sampler
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen 35988b2dba axi_hdmi_rx: Fix packed 422 mode
Currently the hdmi_de_int signal is asserted one clock cycle too early in
packed 422 mode. As a result the EAV sequence ends up in the first pixel
and every other pixel is off by one.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen fa15f8d0b5 axi_hdmi_rx: Add full range support to the TPM
Check for both full range and limited range test-pattern sequences and only
if both don't match assert the tpm_oos signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen fcb841d3e5 axi_hdmi_rx: Move TPM to its own module
Move the test pattern matcher to its own module. This makes it easier to
use it in other configurations as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen ab6ea2c824 axi_hdmi_rx: Drop TPG enable from register map
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen a2a4f3402c up_hdmi_rx: Fix TPM OOS clear
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen c372064302 Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Istvan Csomortani 4744fca18e axi_ad9361: Bring up the tdd_enable bit
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 14:59:32 +03:00
Istvan Csomortani a497dcabb5 axi_ad9361: Bring up the tdd_enable bit
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 13:52:00 +03:00
Lars-Peter Clausen 23034965c8 axi_hdmi_tx_es: Drop strange port initializers
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
Lars-Peter Clausen cb03152f1f axi_hdmi_tx: Don't accidentally send control characters in embedded sync mode
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
Lars-Peter Clausen cf6052e2a8 axi_hdmi_tx: Add control to bypass chroma sub-sampler
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
Lars-Peter Clausen bc4bb111d9 axi_hdmi_rx: Fix packed 422 mode
Currently the hdmi_de_int signal is asserted one clock cycle too early in
packed 422 mode. As a result the EAV sequence ends up in the first pixel
and every other pixel is off by one.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
Lars-Peter Clausen 13c122f1a1 axi_hdmi_rx: Add full range support to the TPM
Check for both full range and limited range test-pattern sequences and only
if both don't match assert the tpm_oos signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Lars-Peter Clausen 4503402eef axi_hdmi_rx: Move TPM to its own module
Move the test pattern matcher to its own module. This makes it easier to
use it in other configurations as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Lars-Peter Clausen d6c64e031f axi_hdmi_rx: Drop TPG enable from register map
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Lars-Peter Clausen 542d64bb5a up_hdmi_rx: Fix enable control
Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Lars-Peter Clausen 231a21548c up_hdmi_rx: Fix TPM OOS clear
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Rejeesh Kutty 185e489802 cpack- signaltap mess 2015-06-29 16:31:53 -04:00
Adrian Costina caabb9444a axi_mc_speed: Removed unneded constraints 2015-06-29 16:53:39 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Adrian Costina fcc185d769 Makefile: Updated makefiles
- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
2015-06-25 14:59:34 +03:00
Istvan Csomortani c9d976d4f7 axi_hdmi_rx: Fix alignment issue on packed formats
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
2015-06-24 12:47:15 +03:00
Istvan Csomortani 1abd1a46b1 axi_hdmi_rx: Fix synchronization issues 2015-06-24 12:47:02 +03:00
Istvan Csomortani c0dd80ccee axi_hdmi_rx: Fix alignment issue on packed formats
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
2015-06-24 12:43:55 +03:00
Rejeesh Kutty 281a47c117 bsplit- altera version, avalon needs a clock 2015-06-24 05:31:08 -04:00
Rejeesh Kutty f4a1a5817c jesd-align: allow sof pass through -- qsys can only do 1 src-dest 2015-06-24 05:31:06 -04:00
Rejeesh Kutty e1b1e1bc2c ad9250- update to use alt ip interface script 2015-06-24 05:31:04 -04:00
Istvan Csomortani 00bc48bc24 axi_hdmi_rx: Fix synchronization issues 2015-06-24 11:03:39 +03:00
Adrian Costina 4e30a5b0bf axi_ad9250: Updated altera core to work with axi4lite interface 2015-06-23 14:29:23 +03:00
Adrian Costina c9e152e500 axi_ad9250: Updated altera core to work with axi4lite interface 2015-06-23 14:28:02 +03:00
Rejeesh Kutty 3e5a5504a7 library/jesd-align- remove signaltap interface 2015-06-19 14:33:03 -04:00
Rejeesh Kutty af2ffbe0a0 library/cpack- add signaltap 2015-06-19 14:33:02 -04:00
Rejeesh Kutty ac6e28c461 library/common: add altera signaltap 2015-06-19 14:33:01 -04:00
Rejeesh Kutty 8a52631189 libary: util_jesd_align- signal tap interface 2015-06-19 14:32:57 -04:00
Rejeesh Kutty 7e08ff0422 library: added util_jesd_xmit 2015-06-19 14:32:56 -04:00
Istvan Csomortani ad743c8403 axi_ad9434: This IP core does not have 'data underflow' port 2015-06-18 16:51:42 +03:00
Adrian Costina d137811952 util_gmii_to_rgmii: Updated core so that it has an option to include a delay controller.
It also allows to configure the fixed delay value so that no additional constraints are needed
The default value of 18 seems to work very well(450mbps tx / 640 mbps rx) on the motor control platform used for tests
2015-06-16 17:39:31 +03:00
Rejeesh Kutty 28e8275a5d library/axi_jesd_gt: split gt lanes 2015-06-12 15:56:03 -04:00
Istvan Csomortani ddc08c960c ad_tdd_control: Connect the reset to all the flops 2015-06-11 12:07:47 +03:00
Rejeesh Kutty 04eb998ff1 axi_jesd_gt: constraints 2015-06-10 14:29:06 -04:00
Rejeesh Kutty e2f4a4c5cf library: make preset registered for timing paths 2015-06-10 13:41:41 -04:00
Rejeesh Kutty df0eaad1e2 gt: constraints 2015-06-10 11:38:15 -04:00
Adrian Costina d6163bea5e axi_jesd_gt: Fixed constraints 2015-06-10 10:56:22 +03:00
Adrian Costina 5e4f572092 axi_ad9122: Fixed constraints 2015-06-10 10:56:03 +03:00
Adrian Costina 8a1f4bf5f6 ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports 2015-06-09 14:21:12 +03:00
Adrian Costina a598e1c614 axi_ad9265: Set default driver value for overflow and underflow ports 2015-06-08 17:50:23 +03:00
Adrian Costina ccf887f0ba axi_ad9643: Set default driver values for overflow, underflow and gpio_in ports 2015-06-08 17:48:41 +03:00
Adrian Costina ded0dd5dbe axi_ad9122: fixed constraints, removed unneded drp reset 2015-06-08 17:45:14 +03:00
Istvan Csomortani 4b08df9ed6 ad9361/tdd: Fix generation of tx_valid_* signals
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:23:32 +03:00
Istvan Csomortani c926daca3a ad9361/tdd: Fix generation of tx_valid_* signals
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:22:21 +03:00
Rejeesh Kutty ce60056cd5 wfifo: async reset for cpu side 2015-06-05 12:44:04 -04:00
Rejeesh Kutty ab1f9bed10 wfifo: remove srl from sync registers 2015-06-05 12:44:04 -04:00
Rejeesh Kutty da8915296b pack: ip scripts 2015-06-05 09:20:08 -04:00
Rejeesh Kutty 6338dfd8b7 ad9361: ip defaults & rst output 2015-06-05 09:19:39 -04:00
Rejeesh Kutty cb0324c2b1 wfifo: multi-channel option 2015-06-05 09:19:05 -04:00
Istvan Csomortani 2e877389b2 ad9361_tdd: Some naming and hierarchical changes 2015-06-04 18:09:49 +03:00
Istvan Csomortani 3b1ea7e528 axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
598ece4c8d
2015-06-04 18:09:47 +03:00
Rejeesh Kutty 6548bcd71f axi_ip- constraints: add rst path 2015-06-04 10:53:13 -04:00
Rejeesh Kutty e02273781f ad_rst- non lpm version 2015-06-04 10:53:12 -04:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Adrian Costina 2b5abf74d7 util_upack: Show upack_valid only if the channel is activated 2015-06-02 11:36:06 +03:00
Rejeesh Kutty 297e885981 library- drp moved to up-clock domain 2015-06-01 14:52:52 -04:00
Rejeesh Kutty e7470036bf library- drp moved to up clock 2015-06-01 13:39:26 -04:00
Rejeesh Kutty c6ebab7393 library- drp moved to up clock 2015-06-01 13:39:26 -04:00
Rejeesh Kutty aa24c442f5 a10gx- no-ddr 2015-06-01 11:00:01 -04:00
Rejeesh Kutty d7b68c39ef altera- sdc 2015-06-01 10:59:59 -04:00
Rejeesh Kutty 2a0bdbebf2 altera- sdc 2015-06-01 10:59:58 -04:00
Rejeesh Kutty 92fc0e050d altera- common sdc 2015-06-01 10:59:57 -04:00
Adrian Costina 83df53d9bf adc_common: Updated version because the delay registers have been changed 2015-05-25 17:18:14 +03:00
Adrian Costina 1ef83bd88b axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly 2015-05-23 00:16:27 +03:00
Istvan Csomortani 660c84e01c axi_ad9434 : Update the IO delay interface 2015-05-22 19:47:09 +03:00
Rejeesh Kutty 0c6ef203c0 iobuf: do is a system-verilog keyword 2015-05-21 14:06:13 -04:00
Rejeesh Kutty dc2eeebf2f upack: gen-name 2015-05-21 14:06:12 -04:00
Rejeesh Kutty 5c6340e927 dmac: clock-typo 2015-05-21 14:06:11 -04:00
Rejeesh Kutty e05ff26406 ad9144: ddata-typo 2015-05-21 14:06:09 -04:00
Rejeesh Kutty 8d78217f7b ad9680: missing prot. ports 2015-05-21 14:06:08 -04:00
Rejeesh Kutty 4c6a3afc88 ad9144: missing prot. ports 2015-05-21 14:06:06 -04:00
Lars-Peter Clausen a059290cf5 Remove axi_ad7175
This core has been superseded by the SPI Engine framework in combination
with the axi_generic_adc core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen c53f8c15ee Add CN0363 project
Add support for the CN0363 (colorimeter) board connected to the ZED board.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen d43ba44d0f Add util_sigma_delta_spi peripheral
The util_sigma_delta_spi peripheral can be used to seperate the interleaved
SPI bus and DRDY signals for a ADC from the Analog Devices SigmaDelta
family.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen e6b58e8a20 Add SPI Engine framework
SPI Engine is a highly flexible and powerful SPI controller framework. It
consist out of multiple sub-modules which communicate over well defined
interfaces. This allows a high degree of flexibility and re-usability while
at the same time staying highly customizable and easily extensible.

Currently included are four components:
	* SPI Engine execution module: The excution module is responsible for
	  handling the low-level physical interface SPI logic.
	* SPI Engine AXI interface module: The AXI interface module allows
	  memory mapped acccess to a SPI bus control stream and can be used to
	  implement a software driver that controls the SPI bus.
	* SPI Engine offload module: The offload module allows to store a
	  predefined SPI Engine command and data stream which will be send out
	  when a external trigger signal is asserted.
	* SPI Engine interconnect module: The interconnect module allows to
	  combine multiple control streams into a single stream giving multiple
	  control modules access to a execution module.

For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen a5b452cc27 Add axi_generic_adc core
The axi_generic_adc core is a simple core that doesn't do much more then
implementing the AXI ADC register map and routing the enable and overflow
signals to the farbic.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen 033713ccb5 Add cordic demodulator module
The cordic_demod module takes in phase and data on s_axis interface then
performs a cordic demodulation and outputs the resulting I and Q component
data on the m_axis interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen cefbe3a0ff scripts/adi_ip.tcl: Add option to specify reset interface direction
Allow to specify the direction of the reset signal for a interface, this is
useful if the core itself generates the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen 6b9906b22b Refresh Makefiles
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
Adrian Costina 5ac7ebb8a3 axi_mc_*: Removed delay pins from up_adc_common 2015-05-21 14:03:58 +03:00
Rejeesh Kutty 465f7dff88 library/util_jesd_align -added 2015-05-20 15:38:43 -04:00
Rejeesh Kutty 9762c65868 library- jesd-align port name change 2015-05-20 14:25:21 -04:00
Rejeesh Kutty da0409b5a6 library- qsys components 2015-05-20 11:51:50 -04:00
Rejeesh Kutty 9b425736ac library: altera ip modifications 2015-05-20 10:41:21 -04:00
Rejeesh Kutty d48d3f4aa3 scripts/ip-alt- added 2015-05-20 09:11:18 -04:00
Rejeesh Kutty e918588a4b library: remove axi-min-size parameter 2015-05-19 13:07:48 -04:00
Rejeesh Kutty 4fb1be0672 ad9680: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty af7afd7366 ad9671: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty 09a05fe9d8 ad9652: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty 13156593f8 ad9643: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty c8d3c04a05 ad9625: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty f53204f9f9 ad9467: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty fe0ceb2530 delay-cntrl updates 2015-05-18 15:23:10 -04:00
Rejeesh Kutty 304a202d67 delay-cntrl updates 2015-05-18 14:57:05 -04:00
Rejeesh Kutty 2e257db109 delay-cntrl updates 2015-05-18 14:53:24 -04:00
Rejeesh Kutty 0877c252ad delay-cntrl changes 2015-05-18 14:28:20 -04:00
Rejeesh Kutty 2bad47cf4f delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Rejeesh Kutty 6e047f78c6 delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Adrian Costina 2c1719095d util_axis_resize: Changed _ip.tcl format to the standard format 2015-05-18 17:25:07 +03:00
Adrian Costina c19749361d Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Istvan Csomortani a07d11c3e9 axi_ad9361_tdd: Define control bits for continuous receive/transmit 2015-05-14 17:21:32 +03:00
Adrian Costina c9c05e21c2 axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis 2015-05-13 16:34:06 +03:00
Istvan Csomortani 7c9bc40c75 axi_ad9361&TDD: Update TDD
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
Rejeesh Kutty a1d680ee6b ad9680- add hw tcl 2015-05-12 15:06:42 -04:00
Rejeesh Kutty 833a3de6b5 ad9680- add hw tcl 2015-05-12 15:06:39 -04:00
Rejeesh Kutty 48c769d431 ad9144- add hw tcl 2015-05-12 14:40:38 -04:00
Rejeesh Kutty 553f89f59d ad9144- add hw tcl 2015-05-12 14:39:57 -04:00
Rejeesh Kutty 4553de3ffa ad9361- align hold 2015-05-11 11:55:01 -04:00
Istvan Csomortani 9934cce5d2 util_dacfifo: Add CDC logic for dma_lastaddr register. 2015-05-11 12:20:46 +03:00
Istvan Csomortani 2e7135c3c2 axi_ad9361_tdd: Initial commit.
Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
Adrian Costina 14e23b106c axi_ad9361: changed device interface module for Altera to have the same inputs as the one for Xilinx 2015-05-08 17:43:10 +03:00
Rejeesh Kutty 12ed393d39 ad9361- framing modifications 2015-05-07 15:13:18 -04:00
Rejeesh Kutty a68539edf1 ad9361- framing modifications 2015-05-07 15:13:17 -04:00
Rejeesh Kutty 176a4a4b76 ad9361: add ddr-edgesel 2015-05-06 16:58:50 -04:00
Rejeesh Kutty a8534a9c02 ad9361: add ddr-edgesel 2015-05-06 16:58:49 -04:00
Rejeesh Kutty 32f7e98afd ad9361: add ddr-edgesel 2015-05-06 16:58:47 -04:00
Adrian Costina 670850183b axi_hdmi_tx: Updated constraints as in fmcomms2/zc702 project they were not correctly applied 2015-05-06 18:53:19 +03:00
Istvan Csomortani a7c96fdac8 util_dacfifo: General clean up of the IO, input/output data has the same width 2015-05-06 16:32:44 +03:00
Istvan Csomortani 0613dca0b7 axi_dmac: Move the 'axis_xlast' logic into the dest_axi_stream module 2015-05-06 16:10:28 +03:00
Adrian Costina 949abcdc8f Makefile: Updated makefiles so that the project recipe does not depend on lib 2015-05-06 14:58:29 +03:00
Istvan Csomortani 65af205d6b axi_dmac: Add axis_last control signal to the Master AXI Streaming interface
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
2015-05-06 13:54:31 +03:00
Adrian Costina 233cc111d2 util_pmod_adc: Used generated clock for the ADC SPI. Works by default at 6.25MHz 2015-05-05 23:33:13 +03:00
Adrian Costina 3517b6941c adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale 2015-05-05 10:06:26 +03:00
Rejeesh Kutty 707b285669 prcfg: bb def 2015-05-04 10:24:13 -04:00
Adrian Costina be32715ab3 axi_adcfifo: Updated constraints 2015-04-30 14:23:24 +03:00
Adrian Costina d623f77453 axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
Adrian Costina 463c4d4d28 util_wfifo: Added constraint for the resetn path 2015-04-30 12:05:02 +03:00
Adrian Costina 392ba31a07 axi_hdmi_rx: Updated constraints 2015-04-30 12:04:15 +03:00
Adrian Costina 288b9cccff Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file 2015-04-28 15:22:37 +03:00
Adrian Costina a7a2d194e9 axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core 2015-04-28 15:04:18 +03:00
Adrian Costina c36186f75a axi_ad9643: Added adc_rst output 2015-04-28 14:52:24 +03:00
Adrian Costina 8ee3f64a65 axi_ad9265: Added adc_rst output 2015-04-28 14:51:14 +03:00
Adrian Costina 67c581cef8 util_wfifo: Updated to be used with adc_rst from the adc_clk clock domain 2015-04-28 14:50:00 +03:00
Adrian Costina 1ad87aa27c util_wfifo: Added constraints 2015-04-27 11:19:56 +03:00
Adrian Costina 81d4e1d9b1 axi_clkgen: Updated constraints 2015-04-27 11:19:15 +03:00
Adrian Costina d950f5ffcd axi_ad9122: Updated constraints 2015-04-27 11:18:52 +03:00
Istvan Csomortani 9fba4cb2ef util_dacfifo: Add support for Slave AXI stream interface.
The FIFO can be initialized through an AXI stream interface too.
2015-04-27 10:40:55 +03:00
Lars-Peter Clausen 3a02998e9a axi_ad9152/axi_ad9152_ip.tcl: Fix typo
axi_ad9152_constr.v -> axi_ad9152_constr.xdc

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-24 09:41:43 +02:00
Adrian Costina a9924e6401 util_gmii_to_rgmii: Added constraints 2015-04-23 16:53:57 +03:00
Adrian Costina bd06bae8c2 library: Modified the adi_ip.tcl script
The constraints processing order changed to "late" instead of "early", in order for all the clocks in the system to be already created when the IP constraints are applied
2015-04-23 14:31:23 +03:00
Adrian Costina a61a195e3f Makefiles: Updated makefiles to add the new constraints as dependecies 2015-04-23 11:16:39 +03:00
Adrian Costina d42c0bc431 axi_jesd_gt : Added CDC and reset constraints 2015-04-23 11:03:51 +03:00
Adrian Costina 1b4e6bdc80 axi_mc_speed : Added CDC and reset constraints 2015-04-23 10:50:49 +03:00
Adrian Costina 6d28d217f1 axi_mc_current_monitor: Added CDC and reset constraints 2015-04-23 10:49:43 +03:00
Adrian Costina d0b2d531bc axi_mc_constroller: Added CDC and reset constraints 2015-04-23 10:47:35 +03:00