zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
3,775 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

2 Commits (0e5a24ee7cab98020358b3360b8ed1f14395aa55)

Author SHA1 Message Date
Lars-Peter Clausen f319d1b5d4 axi_clkgen: Propagate clock settings to output pins 
Calculate the output clock frequencies based on the input clock frequencies
and the default divider settings and configure the output clock pins
accordingly. This allows connected peripherals to infer the frequency of
the clock.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-20 20:36:33 +02:00
Lars-Peter Clausen af913863d4 axi_clkgen: Infer CLKIN period 
Instead of having to manually specify the input clock period infer the
values from the block design. This means that less configuration parameters
need to be changed if the clock input frequency changes.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-20 20:36:15 +02:00