On Arria10 there are 6 transceivers in a single bank. If more than 6
transceivers are used these will end up in multiple banks.
The ATX PLL can directly connect to the transceivers in the same bank
through the 1x clock network. To connect to transceivers in another bank it
has to go through a master clock generation block (MCGB) and the xN clock
network.
Add support for instantiating the MCGB if more than 6 lanes are used. In
this case the first 6 transceivers will still have a direct connection to
the PLL while all other transceivers will be clocked by the MCGB.
Note that this requires that the first 6 transceivers are all in the same
bank.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For a proper reset synchronization, the asynchronous reset signal should
be connected to the reset pins of the two synchronizer flop, and the
data input of the first flop should be connected to VCC.
In the first stage we're synchronizing just the reset de-assertion, avoiding
the scenario when different parts of the design are reseting at different time,
causing unwanted behaviours.
In the second stage we're synchronizing the reset assertion.
The module expects an ACTIVE_HIGH input reset signal, and provides an ACTIVE_LOW
(rstn) and an ACTIVE_HIGH (rst) synchronized reset output signal.
Fix the read side of the CDC data FIFO. The read address generation did not
function correctly.
Redesign the read side of the FIFO, and make sure that it becomes empty after
the DMA transfer ends; and never get stock in a cyclic mode.
Some designs choose to swap the positive and negative side of the of the
JESD204 lanes. One reason for this would be because it can simplify the
PCB layout. The polarity is in most cases also only applied to a subset of
the used lanes.
Add support for this to the adi_jesd204 and jesd204_phy for Altera modules.
This done by adding new parameter to the modules that allows to specify a
per lane polarity inversion. Each bit in the parameter corresponds to one
lane. If the bit is set the polarity is inverted for his lane. E.g. setting
the parameter to 0xc will invert the 3rd and 4th lane.
The setting is forwarded depending on whether soft or hard PCS is used to
either the soft PCS module or the transceiver block itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the individual IP core dependencies are tracked inside the
library Makefile for Xilinx IPs and the project Makefiles only reference
the IP cores.
For Altera on the other hand the individual dependencies are tracked inside
the project Makefile. This leads to a lot of duplicated lists and also
means that the project Makefiles need to be regenerated when one of the IP
cores changes their files.
Change the Altera projects to a similar scheme than the Xilinx projects.
The projects themselves only reference the library as a whole as their
dependency while the library Makefile references the individual source
dependencies.
Since on Altera there is no target that has to be generated create a dummy
target called ".timestamp_altera" who's only purpose is to have a timestamp
that is greater or equal to the timestamp of all of the IP core files. This
means the project Makefile can have a dependency on this file and make sure
that the project will be rebuild if any of the files in the library
changes.
This patch contains quite a bit of churn, but hopefully it reduces the
amount of churn in the future when modifying Altera IP cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In cases when a shallow FIFO is requested the synthesizer infers distributed RAM
instead of block RAMs. This can be an issue when the clocks of the FIFO are
asynchronous since a timing path is created though the LUTs which implement the
memory, resulting in timing failures. Ignoring timing through the path is not a
solution since would lead to metastability.
This does not happens with block RAMs.
The solution is to use the ad_mem (block RAM) in case of async clocks and letting
the synthesizer do it's job in case of sync clocks for optimal resource utilization.
The dma_last_beats is used by the Avalon Memory Mapped interface
controller, to define the last burst length.
Its value get stable after the last valid data of the DMA interface, and staying
stable until the positive edge of the DMA's xfer_req.
No need to condition the transfer of this register to avalon clock
domain.
The XFER_END state defines the end of a transaction, when the entire
data set is written or read to/from the DDRx memory.
A transaction can contain multiple Avalon bursts. Make sure that the FSM
goes back into staging phase at the end of each burst; also define a
signals which indicate the end of each burst for control.
The dac_xfer_req should indicate one single thing, that the FIFO is in
read phase. Should not be affected by any signals, which indicates data
validity on any interface. (e.g. dac_valid)
This signal is not used by the device core, its main purpose is to
indicate the state of the interface for a posible intermediat processing
module.
Fix the reset of the dma_mem_waddr (write address register of the CDC
FIFO on DMA's clock domain). This solves the occasional invalid read backs after
multiple re-initialization of the PL_DDR_FIFO.
+ Build both the read and write logic around an FSM
+ Consistent naming of registers and wires
+ Add support for burst lenghts higher than one, current burst lenght
is 64
+ Fix all the bugs, and make it work (first bring up with
adrv9371x/a10soc)
Export the reset signal for the link clock domain. This can be used by
external logic that is in the link clock domain to reset itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Enabling the phase alignment mode of the FPLL seems to break manual
re-calibration, which is required when changing the lane rates. The
calibration seems to select the wrong VCO frequency band and the PLL no
longer locks.
Disable phase alignment mode for now, this has a negative effects on
deterministic latency, but it is better than not working at all.
Waiting for feedback from Altera/Intel on how to make manual re-calibration
work in phase alignment mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
To be able to check the FPLL re-configuration arbitration status from
software enable the avmm_busy flag in the register map.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a wrapper module for Altera/Intel platforms that instantiates and
connects all the components required to for a JESD204 link.
The following components are created:
* Transceiver for each lane
* Transceiver lane PLL (TX only)
* Transceiver reset controller
* Link PLL
* JESD204 link layer processing
* JESD204 link layer processing control interface
* axi_adxcvr link management peripheral
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a wrapper that instantiates the Arria10 Native PHY and configures it
for JESD204 operation. The datapath width is set to 4 octets per beat.
The maximum lane rate that is achievable with hard-logic PCS included in
the PHY is below the requirements of the JESD204 for some of the PHY speed
grades. For projects that require a lane rate that is higher than what the
hard-logic PCS can support a soft-logic PCS module can be instantiated. The
external interface of the jesd204_phy is identical regardless of whether
soft- or hard-logic PCS is used.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In its default configuration the ram_2port module as a read latency of 2
clock cycles. Both the read address as well as the output data are
registered.
This is not the behavior that is expected from the alt_mem_asym module and
causes incorrect behavior and data corruption in the util_adc_fifo.
Disable the data output register to get a read latency of 1 clock cycle.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We know that NUM_OF_LANES will never exceed 255, but the tools don't know
and generate a warning about implicit signal truncation. Make the
truncation explicit to indicate that this is intentional.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The ADI transport layer peripherals expect the first octet to be in the
LSBs and the last octet to be in the MSBs. The Altera JESD204 core orders
the octets the other way around though, first octet in the MSBs and last
octet in the LSBS.
Currently this is handled by having each transport layer peripheral swap
the octets around when it is connected to the Altera JESD204 core.
Change this so that rather than having to do the data swizzling in every in
every transport layer peripheral perform it at the input/output of the link
layer peripheral inside the generated block.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to
the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system
qsys file in the desired order.
Re-work things so that instead the lane mapping is provided through the
TX_LANE_MAP parameter. The parameter specifies in which order logical lanes
are mapped onto the physical lanes.
The appropriate connections are than made inside the core according to this
parameter rather than having to manually connect the signals externally.
In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left
empty.
This change slightly reduces the boiler-plate code that is necessary to
setup the transceiver.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Comments starting with the word altera are interpreted by the Altera tools
to be synthesis attribute assignments. In this case this is just a generic
comment though which results in a warning that the synthesis attribute is
unknown.
Slightly reword the comment to avoid this. This is not pretty, but better
than having the false positive warning show up in the log.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.
Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The clock bridge expects the clock rate to be specified in Hz, but
$m_coreclk_frequency is in MHz. Do the appropriate conversion.
Nothing seems to rely on the clock bridge reporting the correct frequency
at the moment, so this is only a cosmetic change.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In this particular case the behaviour is the same with non-blocking and
blocking assignments, but that could change if the code is modified in the
future. To avoid any potentially issue due to this consistently use
non-blocking assignments.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the ad_ip_intf_s_axi helper function to create the axi4lite slave
interface for memory mapped peripherals. This slightly reduces the amount
of boilerplate code in the peripheral's *hw.tcl
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The axi_adxcvr register map only uses a single 4k page, make this explicit.
This will allow for tighter packaging in the limited available total
register map space.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Lars-Peter Clausen
Istvan Csomortani
AndreiGrozav
Laszlo Nagy
Adrian Costina
Rejeesh Kutty