3 Commits (0d231935ef4e6ace6c0b704edc5eb7b62e755386)

Author	SHA1	Message	Date
Adrian Costina	eda585f0e4	m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2	2017-02-27 14:16:32 +02:00
Adrian Costina	4e62fb0ef3	m2k: Add reset circuitry on the logic_analyzer clock domain	2017-02-13 12:02:11 +02:00
Adrian Costina	b14d740f87	M2K: initial commit	2017-01-31 16:43:40 +02:00