Commit Graph

2774 Commits (0c6c28ed849a6841dae54ef69326b0c1da5f666f)

Author SHA1 Message Date
Laszlo Nagy 0c6c28ed84 jesd204/ad_ip_jesd204_tpl : Add support for 12 lanes 2021-10-06 15:49:56 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Laszlo Nagy 22e1366bfc jesd204/jesd204_rx: Define tie off values for unused ports 2021-10-05 14:09:51 +03:00
Laszlo Nagy aa93c17cdc jesd204/jesd204_tx/jesd204_tx.v: Have FFs initial value, useful for simulation 2021-10-05 14:09:51 +03:00
Laszlo Nagy 1a9e7dbeb4 jesd204:jesd204_versal_gt_adapter_rx/tx: Add adapter for Versal transceiver IP 2021-10-05 14:09:51 +03:00
Laszlo Nagy 4d12c4d99a scripts/adi_xilinx_device_info_enc.tcl: Add Versal support 2021-10-05 14:09:51 +03:00
Laszlo Nagy 2b242bf06f scripts/adi_ip_xilinx.tcl: Enable auto family support
Some IPs like JESD link layer were marked as not supported on Versal devices by
the current flow while other not (e.g. TPL).
The auto family support seems to workaround this issue.
2021-10-05 14:09:51 +03:00
Laszlo Nagy d94ec80e08 Update README.md
Correct the  ZCU102 PL DDR memory controller interface width and speed based on available options of the MIG
2021-10-05 11:59:51 +03:00
David Winter 0e8f55b2d7 data_offload: Fix oversized inputs in TX mode
This commit fixes an issue in situations where we provide an oversized
transaction to the data offload in TX mode. Previously, the data offload
would stop accepting new data (wr_ready <= 0) after filling up the
internal storage, and get stuck waiting for the input transaction to
end, thus locking up the device.

This commit addresses that issue by allowing the data offload to consume
the full input transaction, even if the tail of the buffer will be
truncated in the output.

Signed-off-by: David Winter <david.winter@analog.com>
2021-09-29 18:33:11 +03:00
Filip Gherman 7ed4955661 axi_adxcvr_ip.tcl util_adxcvr_ip.tcl: Fixed asynchronous resets critical warnings in XCVR 2021-09-28 04:53:02 +03:00
stefan.raus cfe0c0ced5 adi_project_xilinx.tcl, adi_ip_xilinx.tcl: update version to 2021.1
Update vivado version from 2020.2 to 2021.1 in projects and library scripts.
2021-09-24 12:11:11 +03:00
Mihaita Nagy 1fe0d5f8e0 data_offload: Fix timing violation 2021-09-22 12:18:33 +03:00
David Winter cdb9a0af2b data_offload: Add sync to cyclic mode
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-21 09:06:03 +03:00
AndreiGrozav 76cd5581bc axi_pwm_gen: Add config in soft reset option 2021-09-17 11:50:46 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Robin Getz b38747cefc Make system: Be explicit in license that cover the make/build system
The build system is covered under a 1 Clause BSD license. Make sure
users are aware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:50:53 +03:00
Robin Getz 12a3f8799e JESD204 Interface Framework : add logo
Add a small logo for branding purposes.

Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:49:52 +03:00
David Winter 1766b42a93 ad_mem_asym: Add option to control cascade layout
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-15 12:27:49 +03:00
Iacob_Liviu 6763ddcda9 spi_engine_execution: Fix cs signal generation
The cs signal can now accept the IOB TRUE attribute.
2021-09-13 11:39:02 +03:00
David Winter 0392013bd2 util_tdd_sync: Narrow scope of false path to D pin
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:24 +03:00
David Winter 7423ecae14 data_offload: Improve external synchronization
This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.

The default value retains the old behavior.

Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:01 +03:00
Filip Gherman 0372ce1821 axi_adxcvr:util_adxcvr: Correctly defined resets. 2021-09-08 11:51:59 +03:00
LIacob106 16a93a804b adrv9001[intel]: Add second pair of DMAs
fix observations for PR
2021-09-01 15:04:14 +03:00
alin724 f8c82c611d axi_adrv9001: Add support for symbol operation mode on Xilinx devices
Add CMOS support for the interface for the following symbol modes on Xilinx devices:

A              B  C       D                     E       F      G            H
CSSI__1-lane   1  16/8    80(SDR)/160(DDR)      80      -      SDR/DDR      SDR/DDR->4/2(C=16), 2/1(C=8)

Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate

CSSI - CMOS Source Synchronous Interface
2021-08-17 15:33:06 +03:00
Laszlo Nagy 8afc03abab jesd204/ad_ip_jesd204_tpl_dac: Intel: Add support for AD916x preset files 2021-08-16 07:22:50 +03:00
stefan.raus 1f24344620 Update Quartus version to 20.4
Update quartus compilation tools from 20.1 to 20.4.
Remove hardcoded version from axi_adrv9001 ip.
2021-08-12 11:15:01 +03:00
David Winter 235542cac9 data_offload: Fix support for > 4 GiB of storage
This commit changes the transfer length register to work in increments of
64 bytes and without offset. The true transfer length can now be
determined by multiplying the value of the transfer_length register with
64.
A value of zero is interpreted as a request for all available storage.

Additionally, this commit fixes an off by one issue that was discovered
during testing of the RX path.

Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 25038ccb4d data_offload: Fix MEM_SIZE parameter width
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 58953ff40d data_offload: Fix m_axis output stability issue
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 2b55c7453b data_offload: Fix duplicated output samples
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 04f2d19d4b data_offload: Fix data_offload getting stuck on oscillating m_saxis_ready
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 0af50d3f72 data_offload: Fix oneshot mode
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 66748510ea data_offload: write_fsm: Always transition out of idle on high init_req
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 9faef440b2 data_offload: Bump hdl version
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter a89d0e6176 data_offload: Fix AXI register map
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 537a284115 data_offload: Fix readme images
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
Istvan Csomortani 6516b09a31 data_offload: Update README and generic block design 2021-08-06 11:55:24 +03:00
Istvan Csomortani 26518cdace data_offload: Add block diagrams 2021-08-06 11:55:24 +03:00
Istvan Csomortani 9b1108ea87 data_offload: Flush the DMA if the transaction size is bigger than the storage 2021-08-06 11:55:24 +03:00
Istvan Csomortani c82b0fb420 data_offload: Delete fifo_dst_rlast 2021-08-06 11:55:24 +03:00
Istvan Csomortani 0436a82f4e data_offload: Fix alignment of write last beat and write full 2021-08-06 11:55:24 +03:00
Istvan Csomortani 378daf031c data_offload: Improve timing in regmap 2021-08-06 11:55:24 +03:00
Istvan Csomortani c27a0e4add data_offload: Fix fifo_dst_ready generation 2021-08-06 11:55:24 +03:00
Istvan Csomortani 86b611c1f7 data_offload: Initial commit 2021-08-06 11:55:24 +03:00
Istvan Csomortani 6e97803437 ad_axis_inf_rx: Initialize output ports to avoid X propagation in simulation 2021-08-06 11:55:24 +03:00
Istvan Csomortani b9ac3a78a9 interfaces: Add XFER_REQ to fifo_rd_rtl.xml 2021-08-06 11:55:24 +03:00
Istvan Csomortani 157a8dee17 util_fifo2axi_bridge: Initial commit 2021-08-03 23:02:17 +03:00
Istvan Csomortani 0959c2bcad util_axis_fifo_asym: Initial commit 2021-08-03 23:02:17 +03:00
Nick Pillitteri 1543eb8881 axi_generic_adc: pass in number of channels instantiated to up_adc_common. Allows drivers/iio/adc/ad_adc.c driver to be used with this core.
Signed-off-by: Nick Pillitteri <njpillitteri@gmail.com>
2021-08-02 13:10:26 +03:00
stefan.raus 9d5de2fc21 Update Vivado version to 2020.2
Update vivado version to 2020.2:
 - update default vivado version from 2020.1 to 2020.2
 - add conditions to apply specific contraints only in Out Of Context mode.
 - update DDR controler parameters for vcu118 and kcu105 dev boards
2021-07-29 14:06:42 +03:00