acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
...
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
51e35e081f
fmcadc2: update adcfifo/dacfifo
2019-01-23 14:45:45 +02:00
2293374307
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs
...
The affected projects are:
- FMCADC2/VC707 - 16Mb
- FMCADC5/VC707 - 16Mb
- DAQ2/ZC706 - ADC@1GB and DAC@8Mb
- DAQ2/KC705 - ADC@4Mb and DAC@4Mb
- DAQ2/VC707 - ADC@8Mb and DAC@8Mb
- DAQ2/KCU105 - ADC@4Mb and DAC@4Mb
- DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb
- DAQ3/ZC706 - ADC@1GB and DAC@8Mb
- DAQ3/KCU105 - ADC@4Mb and DAC@4Mb
- DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb
- ADRV9371x/KCU105 - DAC@8Mb
- ADRV9371x/ZCU102 - DAC@16Mb
2018-08-21 11:44:05 +03:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
343d0472d4
fmcadc2: Move GT setting to common/system_bd.tcl
2017-02-16 14:56:25 +02:00
07184b31d2
fmcadc2: Define default clock selection for Xilinx GTs
2017-02-16 12:35:24 +02:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
bb185296d7
fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples.
...
The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
2015-04-23 18:00:00 +03:00
19e4950b72
renamed to match official names
2014-12-08 10:44:15 -05:00
sergiu arpadi
Laszlo Nagy
Istvan Csomortani
Rejeesh Kutty