f34b561e19
daq3: Parameterize JESD204 configuration values
...
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:47:01 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
...
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
2d825d8b7c
daq3_zc706: Change implementation strategy
2019-02-12 10:43:46 +02:00
b7ca17f02b
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 12:06:50 +03:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
661413627f
daq3- round about way to avoid ip getting locked
2017-01-20 15:55:33 -05:00
ad96c5e881
daq3/zc706: Change the speed grade of the FPGA to 3
2016-12-06 15:24:23 +02:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
caa0e27bd6
daq3: 2014.4 updates
2015-03-19 12:45:54 -04:00
e81327b794
daq3_zc706: Add constraint file for PLDDR
2014-12-18 10:08:33 +02:00
2600b1f359
daq3: tx interleave and dma fifo axi streaming
2014-10-15 14:51:04 -04:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
525373fc04
daq3: daq2 copy
2014-10-06 10:34:00 -04:00
Dan Hotoleanu
Adrian Costina
Istvan Csomortani
AndreiGrozav
Rejeesh Kutty
Lars-Peter Clausen