Commit Graph

58 Commits (0c0617d49ee4bc499ae77b2983fcf5e406d6e77a)

Author SHA1 Message Date
Laszlo Nagy 501903bc81 adrv9371x/zc706: Hook up un-gated ref clock to fabric 2022-02-15 11:09:37 +02:00
Filip Gherman 6a92bd5925 adrv9371x: Parameterize JESD204 configuration values 2022-01-12 16:05:48 +02:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
AndreiGrozav 44deaadb4a adrv9371: Add decimation and interpolation filters 2019-08-20 16:24:47 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
Laszlo Nagy b98eb28dca adrv9371: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy e864786d3a adrv9371: use generic TPL
Use the generic TPLs for a better scalability to ease lane number
reductions.
2019-01-14 17:21:00 +02:00
Lars-Peter Clausen aed8478d10 adrv9371x: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
Laszlo Nagy fa7c85a9eb all: Drive undriven input signals, complete interface
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top

fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]

The change excludes the generated system.v and Xilinx files.
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Lars-Peter Clausen 377247a434 Regenerate project Makefiles using the new shared Makefile includes
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
AndreiGrozav 502989c25f jesd_rst_gen:constraints: Remove invalid false path definitions
The constraint where added to remove timing problems on the reset path.

The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.

Projects affected by this change:
  - daq3
  - adrv9739
  - ad6676evb
  - fmcadc5
  - daq2/kcu105
  - fmcadc2
  - adrv9371x
  - fmcomms11/zc706
  - fmcjesdadc1
2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
Michael Hennerich 2e59a70cdd adrv9371: Increase FCLK2 to 200MHz to support max sampling rates
This fixes an issue seen when using 307.2 MSPS on the Observation RX.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2018-01-09 15:20:06 +01:00
Istvan Csomortani 700ed156ab [axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx 2017-09-25 08:56:40 +01:00
AndreiGrozav a64998c3ff adrv9371x: Separate ps7 assignaments from common
Move the assignaments/connections for ps7 from common/adrv9371_bd
to zc706/system_bd
2017-08-22 15:37:59 +03:00
Lars-Peter Clausen 0360e8587e Connect JESD204 interrupts
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Lars-Peter Clausen a7e72245ff adrv9371: Convert to ADI JESD204 core
Convert the ADRV9371 project to the ADI JESD204 link layer cores. The
change is very straight forward, but a matching change on the software side
is required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Rejeesh Kutty fb4a583613 projects/system_bd- adc/dac fifo board designs 2017-02-27 16:06:39 -05:00
Rejeesh Kutty c598e84258 remove processing order (no clock def dependency) 2017-02-22 16:02:08 -05:00
Rejeesh Kutty edd5e9570f file renamed; sed output; fingers crossed 2017-02-22 15:56:37 -05:00
Istvan Csomortani 7008c641b5 axi_adrv9371/zc706: Constraints update
From source *jesd_rstgen* is a false path for TX and RX_OS too.
2016-11-11 10:35:09 +02:00
Istvan Csomortani 35c2dd5d6d adrv9371x/zc706: Fix constraints 2016-11-09 16:34:08 +02:00
Rejeesh Kutty 7290bcc81a hdlmake- updates 2016-09-29 11:50:58 -04:00
Rejeesh Kutty 4950c6c773 adrv9371x - xcvr updates 2016-09-29 11:50:58 -04:00
Istvan Csomortani 16ee1336c3 Makefile: Update make files 2016-09-15 11:41:06 +03:00
Rejeesh Kutty ce1fed1ce6 dmafifo- adc/dac split 2016-08-16 12:54:39 -04:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00