Commit Graph

2 Commits (0b61df7847e80bb327fc2525ae65305044be2608)

Author SHA1 Message Date
Jorge Marques 55d4215f45 README.md: header, docs info; docs: license, fixes
Add documentation info to the README.md
At adi_hdl_parser.py, filter "_signal_clock" and "_signal_reset"
pseudo buses from component.xml files, append them as description
in the ports table, in the format
"{Bus} [...] is synchronous to this {domain}".
Also, adds collapsible directive

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00
Jorge Marques cf056cf81c docs: add regmap directive
Automate table generation for register maps.
Based on tfcollins' vger python scripts.
There are docs/adi_regmap_*.txt with more than one regmap per file,
so the logic changed to allow that.
Using title tool as the unique identifier now.
It has a global option to set the default state (hidden or visible)
for the collpasible tables.
Also remove CSVs.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00