Update link roles to use the "text <link>" standard sphinx syntax.
Add __pycache__ and _build to .gitignore
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Added the files generated by Quartus Pro 21.2, 20.1 and Platform Designer for each of the versions. The files added are generated and removed by make.
Signed-off-by: Liviu.Iacob <liviu.iacob@analog.com>
Almost all the IPs found in library generate a bd folder when they are built. Updated the .gitignore so that it does not appear as an untracked file.
Also, changes to tracked bd.tcl files (ex:axi_dmac) will still appear as modified files.
Signed-off-by: Liviu.Iacob <liviu.iacob@analog.com>
The scripts are looking for a previous run result, a routed design
checkpoint to use it as a reference during the incremental build flow.
Before clearing the project files, the scrips will save the reference dcp
file in the project folder.
If the reference dcp does not exists the build continues normally.
Proposed workflow:
1. Build your project normally with 'make' or place manually a
reference.dcp file in the Vivado project folder.
2. Do some minor modifications
3. Run the make with the following option:
make MODE=incr
4. Repeat steps 2-3
Using a common IP cache location for all the project will speed up
compile time of common blocks used in base designs. Example a MicroBlaze
core for VCU118 once compiled it will be reused on other projects.
Using a common IP cache will speed up re-compiles of every project in OOC
mode since the cache won't be cleared as with normal compile flow.
The system_db folder is autogenerated and contains all the files that are
generated by the Platform Designer tool.
The extension for Intel binary bitstreams is rbf.
Add both of those to the .gitignore since they should not be under version
control and just end up as clutter in `git status` otherwise.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the individual IP core dependencies are tracked inside the
library Makefile for Xilinx IPs and the project Makefiles only reference
the IP cores.
For Altera on the other hand the individual dependencies are tracked inside
the project Makefile. This leads to a lot of duplicated lists and also
means that the project Makefiles need to be regenerated when one of the IP
cores changes their files.
Change the Altera projects to a similar scheme than the Xilinx projects.
The projects themselves only reference the library as a whole as their
dependency while the library Makefile references the individual source
dependencies.
Since on Altera there is no target that has to be generated create a dummy
target called ".timestamp_altera" who's only purpose is to have a timestamp
that is greater or equal to the timestamp of all of the IP core files. This
means the project Makefile can have a dependency on this file and make sure
that the project will be rebuild if any of the files in the library
changes.
This patch contains quite a bit of churn, but hopefully it reduces the
amount of churn in the future when modifying Altera IP cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Jorge Marques
Iulia Moldovan
Liviu.Iacob
Laszlo Nagy
Istvan Csomortani
Lars-Peter Clausen
Rejeesh Kutty