4 Commits (09ffe42603b278453bc56d736225dae1c4c708d2)

Author	SHA1	Message	Date
Adrian Costina	094872619d	axi_ad9963: Separated adc/dac clock and reset	2017-04-18 12:17:39 +02:00
Adrian Costina	9f8fd5c922	axi_ad9963: updated tx path ... - removed pll for power saving, added serdes circuitry instead	2017-04-18 12:17:39 +02:00
Lars-Peter Clausen	3e0b337eae	axi_ad9963: Remove extra pipeline stages on register read path ... The register read logic is not that complicated that it needs two extra pipeline stages. It can easily be condensed into a single combinatorial and still meet timing with large margins. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2017-04-18 12:17:39 +02:00
Adrian Costina	fb945ac51c	axi_ad9963: Initial commit	2017-01-31 16:18:58 +02:00