fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
343d0472d4
fmcadc2: Move GT setting to common/system_bd.tcl
2017-02-16 14:56:25 +02:00
07184b31d2
fmcadc2: Define default clock selection for Xilinx GTs
2017-02-16 12:35:24 +02:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
0c42e04bc3
fmcadc2: Integrate ad_sysref_gen into the project
2016-12-19 12:16:05 +00:00
c455d2d64f
fmcadc2/vc707: Disabele axi_spi constraint file
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The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:15:44 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
3dceb53984
fmcadc2/vc707: Fix timing violations
2016-12-08 19:51:18 +02:00
8eaae98728
fmcadc2: Updates
2016-12-07 21:43:19 +02:00
170c781d02
hdlmake.pl- updates
2016-12-01 13:52:11 -05:00
daa3df4b96
projects/- xcvr updates
2016-11-22 16:23:05 -05:00
aff45eae5f
fmcadc2: xcvr updates
2016-11-21 18:45:38 +02:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
93fa5aeec3
fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2
2016-09-01 16:11:39 +03:00
2015bcedaa
fmcadc2: Update common design to Vivado 2016.2
2016-08-30 16:42:58 +03:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
b0538a03a2
Make: Update
2016-05-06 16:44:24 +03:00
4863a04132
axi_adc/dacfifo: Split the intergration script file
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Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
2016-05-05 09:53:55 +03:00
be74db656c
ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1:
...
Update system_project.tcl scripts to correctly select the necessary
constraint files
2016-05-04 19:37:33 +03:00
3ca3414522
fmcadc2: Fixed bus data width
2016-05-04 19:20:01 +03:00
9104b2cc60
ad6676evb, fmcadc2, fmcadc4, fmcadc5,...
...
ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
2016-05-04 19:13:25 +03:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
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hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
3006c5a223
make updates
2016-04-11 16:14:59 -04:00
21208ca208
Makefiles: Update Makefiles
2016-03-31 12:37:47 +03:00
98cc7dad7d
fmcadc2: Updated common design to 2015.4
2016-03-15 15:26:05 +02:00
977d9d0624
Merge branch 'hdl_2015_r2' into dev
...
Conflicts:
projects/daq1/common/daq1_spi.v
2016-03-02 13:52:15 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
ce760eb691
fmcadc2- add adf4355 access
2016-02-18 16:17:33 -05:00
9cd0378003
fmcadc2: Added clock constraint for the ADC path
2016-01-22 15:44:04 +02:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
848b51699c
fmcadc2: Updated VC707 project
2015-09-25 17:28:15 +03:00
e764f54426
fmcadc2: Updated ZC706 project
2015-09-25 17:26:54 +03:00
6fbd8dd9a5
fmcadc2: Update projecct to 2015.2.1
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- updated to the new jesd framework
2015-09-25 17:25:32 +03:00
60490c4e2b
fmcadc2: Drop explicit axi_dmac clock synchronicity configuration
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The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:59 +02:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
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Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
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The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
c3ea99d1f8
fmcadc2: Fixed zc706 spi connection
2015-06-19 13:31:59 +03:00
71b5004b25
projects- drp moved to up-clock domain
2015-06-01 14:57:59 -04:00
a6cae6b477
iobuf: do is a system verilog keyword
2015-05-21 14:06:17 -04:00
Rejeesh Kutty
Istvan Csomortani
AndreiGrozav
Adrian Costina
Lars-Peter Clausen