89bd8b44d4
Merge branch 'dev' into hdl_2017_r1
2017-09-26 07:42:19 +01:00
256dd87dd2
common/microzed: Enable PS CLK1 = 200MHz
2017-09-25 15:16:58 +03:00
07f3295638
common/a10soc: Update configuration for emif plddr4 IP
2017-09-25 08:57:26 +01:00
700ed156ab
[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx
2017-09-25 08:56:40 +01:00
3a47567f9c
common/a10gx: Chance SPI frequency from 128KHz to 10 MHz
2017-09-19 18:01:18 +03:00
cafa811c74
adrv9379: Change the DMA clock to 250
2017-09-11 16:52:44 +03:00
58572d746c
arradio/c5soc- rd10102013_979 fix
2017-09-05 12:52:41 -04:00
c3aa3e8a9c
adrv9371: a10soc: Whitespace cleanup
...
Remove some extra end-of-line whitespace.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-05 13:47:49 +02:00
6736aaeca1
arradio- add control/status ports
2017-09-01 14:39:18 -04:00
bb73e7a40f
arradio- add control/status ports
2017-09-01 14:39:18 -04:00
6ce4494002
adrv9379: Initial commit
2017-09-01 17:28:04 +03:00
cb2fd6af73
dm2k: Drive the ADC DMA valid from the trigger extracting core
2017-08-30 18:28:52 +03:00
5bc927ff94
adrv9364/ccbox- input rf protection
2017-08-25 13:30:46 -04:00
dc0a71920c
adrv9361/ccbox- sort gpio - accidental multiple drivers
2017-08-25 13:30:46 -04:00
fd8b524953
adrv9361-ccbox/ccfmc- adl5904/gpio updates
2017-08-25 11:23:56 -04:00
4050f5ae58
adrv9361- add adl5904
2017-08-24 15:47:17 -04:00
e4988aa131
adrv9371x: altera: Convert to ADI JESD204
...
Convert the ADRV9371 project for Intel/Altera platforms to the ADI JESD204
framework.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:55:10 +02:00
d05ed29212
adrv9371x_zcu102: Initial commit
2017-08-22 15:48:03 +03:00
c0da4e6192
adrv9371x_kcu105: Initial commit
2017-08-22 15:41:49 +03:00
1d67036305
adrv9371x/common: Remove ila_adc and ila_os_adc
2017-08-22 15:37:59 +03:00
6fa45bb378
adrv9371x/common: Fix axi_ad9371_dacfifo/dac_rst assignamen
2017-08-22 15:37:59 +03:00
a64998c3ff
adrv9371x: Separate ps7 assignaments from common
...
Move the assignaments/connections for ps7 from common/adrv9371_bd
to zc706/system_bd
2017-08-22 15:37:59 +03:00
b7ce81686a
common/zcu102: Fix ps8 ref clock 0 frequency assignament
2017-08-22 15:37:59 +03:00
41e247d426
common/zcu102: Add gpio_t connections
2017-08-22 15:37:59 +03:00
7fa8498b3a
adrv9371x: DAC_FIFO should get the dma_rst from sys_dma_rstgen
2017-08-22 09:16:21 +01:00
b0b79013f7
fmcomms11: Connect data underflow to the core
2017-08-22 09:16:21 +01:00
d5eedf8356
daq2: Add support for Arria10 SoC platform
...
Add support for the AD-FMCDAQ2-EBZ on the Arria10 SoC development board platform.
In its default configuration the Arria10 SoC development board is not fully
compatible with the AD-FMCDAQ2-EBZ and a slight rework is necessary,
changing the position of four 0 Ohm resistors:
R610: DNI -> R0
R611: DNI -> R0
R612: R0 -> DNI
R613: R0 -> DNI
R620: DNI -> R0
R632: DNI -> R0
R621: R0 -> DNI
R633: R0 -> DNI
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:21:42 +02:00
17d3e3c64b
daq2: daq2_qsys.tcl: Convert to ADI JESD204
...
Convert the DAQ2 project for Intel/Altera platforms to the ADI JESD204
framework.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:21:42 +02:00
ce88b8ba91
daq2: daq2_qsys.tcl: Rework peripheral addresses
...
Rework the peripheral address to match the updated semantics of
ad_cpu_interconnect, which expects that the addresses are in the range of
0x00010000 - 0x001fffff. This includes updating the base addresses as well
as compressing the used address range to fit into the 2Mb window.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:21:42 +02:00
c843a16797
microzed: Add a secondary 200 MHz clock for PS7
2017-08-18 10:14:21 +03:00
cd07ee80aa
hdlmake.pl - updates
2017-08-09 14:09:14 -04:00
4ef784b609
fmcomms2/zc702- pmod1 udc, pmod2 gpio
2017-08-09 14:08:47 -04:00
6cee492d96
fmcomms5/zc702- pmods as gpios
2017-08-09 14:07:58 -04:00
90af9a8f8c
adv7511/zc702- pmods as gpios
2017-08-09 14:07:31 -04:00
c632f4463f
projects/zc702- free pmod gpio for customization
2017-08-09 14:06:26 -04:00
b9683aab40
adrv936x- readme updates
2017-08-08 15:18:43 -04:00
b118c6874e
adrv936x- readme updates
2017-08-08 15:14:16 -04:00
8778986416
adrv936x- readme updates
2017-08-08 15:11:44 -04:00
77275713e9
Update README.md
2017-08-08 14:09:37 -04:00
1c386d4d34
hdlmake.pl- updates
2017-08-07 16:09:20 -04:00
28801f2f37
common: a10soc: Use correct DDR memory reference clock type
...
The DDR memory reference clock on the A10SoC development board is
differential. Currently the EMIF core it is configured for single-ended
configuration, which causes it to generate incorrect IOSTANDARD
constraints. Those incorrect constraints get overwritten again in
system_assign.tcl, so things are working, but this generates a warning when
building the design
Configure the EMIF core correctly and remove the manual constraint overwrite since
they are no longer necessary.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:42:17 +02:00
15c3c96512
ad9361- clkdiv to util_ad9361_divclk
2017-08-07 11:25:55 -04:00
e4d71c99a6
fmcomms5- bd- data flow format
2017-08-07 11:25:55 -04:00
d5d305ec79
fmcadc2: Fix connection between a db port and a net
...
The block design port should always be the first argument of the
ad_connect process call.
2017-08-07 17:00:01 +03:00
d0503536a8
adrv936x- bd.tcl in data flow format
2017-08-04 13:48:22 -04:00
da6adc5477
ad738x_fmc: Supported sample rate is 3MSPS
2017-08-04 15:08:37 +03:00
cff31e242a
ad738x_fmc: Configuration update/fix
...
Configure the spi_engine exectution module to support two
SDI lines for the SPI interface. Clean up the system_top.v.
2017-08-04 14:50:06 +03:00
f933a4cbcd
ad738x_fmc: Initial commit
2017-08-04 14:49:17 +03:00
5c252783e7
m2k: Move ADC hardware gain correction from the AD9963 IP to AXI_ADC_DECIMATE IP
2017-08-04 14:29:27 +03:00
cf25aeacf5
fmcomms2_bd- keep data flow format
2017-08-03 13:41:26 -04:00
Istvan Csomortani
AndreiGrozav
Adrian Costina
Rejeesh Kutty
Lars-Peter Clausen