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22 Commits (07956cfe66bc297193241904e092d4790e8d261f)

Author SHA1 Message Date
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Rejeesh Kutty c277b39796 arradio/c5soc- critical warnings fix 2017-03-20 12:14:13 -04:00
Rejeesh Kutty 4f0d7bd6eb util_wfifo: read after write is complete 2016-07-11 09:59:31 -04:00
Rejeesh Kutty bf0b90229a rfifo/wfifo- qsys ip 2016-05-18 13:24:13 -04:00
Rejeesh Kutty 4fbff45e27 util_wfifo- updates 2016-05-16 12:19:38 -04:00
Istvan Csomortani 900db3d8ed util_wfifo: Fix reset related timing violation 
The memory instance reset connected to ground, rather than connect to dout_rstn.
 2015-09-23 16:36:33 +03:00
Istvan Csomortani 516c59523d util_wfifo: Cosmetic changes. 2015-09-23 16:36:31 +03:00
Adrian Costina 46808c4c41 util_wfifo: Changed some reset for several registers from asynchronous to synchronous for better integration with the FIFO 2015-09-16 18:55:47 +03:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters 
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
 2015-08-19 14:11:47 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Rejeesh Kutty ce60056cd5 wfifo: async reset for cpu side 2015-06-05 12:44:04 -04:00
Rejeesh Kutty cb0324c2b1 wfifo: multi-channel option 2015-06-05 09:19:05 -04:00
Adrian Costina 67c581cef8 util_wfifo: Updated to be used with adc_rst from the adc_clk clock domain 2015-04-28 14:50:00 +03:00
Adrian Costina 6ee9b3a1e2 util_wfifo: Fixed reset 2015-03-25 15:34:21 +02:00
Rejeesh Kutty 36b041ccc0 util_wfifo: port name fixes & doc. 2015-01-06 16:15:42 -05:00
Adrian Costina 2744d0cb37 util_wfifo: Update to implement flip flops 2014-11-17 12:10:21 +02:00
Rejeesh Kutty 403fe1b373 wfifo: read only if ready is asserted 2014-10-31 13:05:17 -04:00
Rejeesh Kutty f0b25c39a3 wfifo: added axi stream support 2014-10-15 14:50:56 -04:00
Rejeesh Kutty e38813fa9f fifo- monitor status signals 2014-06-25 12:15:13 -04:00
Rejeesh Kutty af07f8874f wfifo/rfifo: asynchronous interface 2014-04-10 14:01:40 -04:00
Rejeesh Kutty f9dfd944c9 library/util_fifo: updates for read side 2014-03-10 14:48:14 -04:00
Rejeesh Kutty d6256e9e29 library: dds and dcfilter changes, added fifo wrappers 2014-03-10 11:11:16 -04:00