Commit Graph

2187 Commits (078a7fffc8de2ab113f63764463539c4907071d5)

Author SHA1 Message Date
Lars-Peter Clausen 0a30cdbf99 Add util_cpack2 core
The util_cpack2 core is similar to the util_upack core. It packs, or
interleaves, a data from multiple ports into a single data. Ports can
optionally be enabled or disabled.

On the input side the cpack2 core uses a multi-port FIFO interface. There
is a single data write signal (fifo_wr_en) for all ports. But each port can
be individually enabled or disabled using the enable signals.

On the output side the cpack2 core uses a single port FIFO interface. When
data is available on the output interface the data write signal
(packed_fifo_wr_en). Data on the packed_fifo_wr_data signal is only valid
when packed_fifo_wr_en is asserted. At other times the content is
undefined. The cpack2 core offers no back-pressure. If data is not consumed
when it is made available it will be lost.

Data from the input ports is accumulated inside the cpack2 core and if
enough data is available to produce a full output vector the data is
forwarded.

This core is build using the common pack infrastructure. The core that is
specific to the cpack2 core is mainly only responsible for generating the
control signals for the external interfaces.

The core is accompanied by a test bench that verifies correct behavior for
all possible combinations of enable masks.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 90540bf447 Add util_upack2 core
The util_upack2 core is similar to the util_upack core. It unpacks, or
deinterleaves, a data stream onto multiple ports.

The upack2 core uses a streaming AXI interface for its data source instead
of a FIFO interface like the upack core uses.

On the output side the upack2 core uses a multi-port FIFO interface. There
is a single data request signal (fifo_rd_en) for all ports. But each port
can be individually enabled or disabled using the enable signals.

This modified architecture allows the upack2 core to better generate the
valid and underflow control signals to indicate whether data is available
in a response to a data request.

If fifo_rd_en is asserted and data is available the fifo_rd_valid signal
are asserted in the following clock cycle. The enabled fifo_rd_data ports
will be contain valid data during the same clock cycle as fifo_rd_valid is
asserted. During other clock cycles the output data is undefined. On
disabled ports the data is always undefined.

If no data is available instead the fifo_rd_underflow signal is asserted in
the following clock cycle and the output of all fifo_rd_data ports is
undefined.

This core is build using the common pack infrastructure. The core that is
specific to the upack2 core is mainly only responsible for generating the
control signals for the external interfaces.

The core is accompanied by a test bench that verifies correct behavior for
all possible combinations of enable masks.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 7f74e5cc39 Add util_pack infrastructure
Pack and unpack operations are very similar in structure as such it makes
sense for pack and unpack core to share a common infrastructure.

The infrastructure introduced in this patch is based on a routing network
which can implement the pack and unpack operations and grows with a
complexity of N * log(N) where N is the number of channels times the number
of samples per channel that are process in parallel.

The network is constructed from a set of similar stages composed of either
2x2 or 4x4 switches. Control signals for the switches are fully registered
and are generated one cycle in advance.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Adrian Costina d4b0f78192 axi_adrv9009: Split DATAPATH parameter in multiple parameters for Intel IP 2018-11-27 15:31:21 +02:00
Adrian Costina a5b7699bd5 axi_adxcvr: Fix typo in initial parameters values 2018-11-16 14:18:33 +02:00
Adrian Costina e1f15f946b axi/util_adxcvr: Add register to control eyescan reset 2018-11-16 14:18:33 +02:00
Adrian Costina b4ea058085 axi_adxcvr: axi_adxcvr_es.v cleanup trailing whitespaces 2018-11-16 14:18:33 +02:00
Adrian Costina 98d3d44fd1 axi_adxcvr: Fix eyescan support for ultrascale plus devices 2018-11-16 14:18:33 +02:00
Istvan Csomortani 46f16f0e99 axi_dmac/tb: Add support for xsim
Add support for Vivado's simulator. By default the run script is using
the Icarus simulator.

If the user want to switch to another simulator, it can be explicitly
specify the required simulator tool in the SIMULATOR variable.
Currently, beside Icarus, Modelsim (SIMULATOR="modelsim") and Vivado's
xsim (SIMULATOR="xsim") is supported.
2018-11-07 12:13:06 +02:00
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-17 10:32:47 +03:00
AndreiGrozav 251ea9471c Remove Xilinx 6 series support
The primitives are not used or supported by the newer versions of Vivado.
2018-10-17 10:06:40 +03:00
Lars-Peter Clausen 8fdd27c605 axi_ad9361: Mark rst output as active high
By default inferred output reset signals have an active low polarity. The
axi_ad9361 rst output signal is active high though. Currently when
connecting it to a input reset with active high polarity will generate an
error in IPI.

Fix this by explicitly marking the polarity of the rst signal as active
high.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-16 15:14:53 +03:00
Istvan Csomortani 65ae466cc9 util_dacfifo: Delete unused registers 2018-10-16 10:29:37 +03:00
Istvan Csomortani d0adbb718a util_dacfifo: Update constraint file
Delete deprecated, old constraints; update the constraint flag from
'hier' to 'hierarchical'.
2018-10-16 10:29:37 +03:00
Lars-Peter Clausen b7ea846c40 ad_ip_jesd204_tpl_dac: Use perfect shuffle helper module
Replace the open-coded instances of a perfect shuffle in the DAC framer with
the new helper module.

Using the helper module gives well defined semantics and hopefully makes
the code easier to understand.

There are no changes in behavior.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-15 15:34:31 +03:00
Lars-Peter Clausen 67f204e10e library: Add perfect shuffle module
The perfect shuffle is a common operation in data processing. Add a shared
module that implements this operation.

Having this in a shared module rather than open-coding every instance makes
sure that there are clear and well defined semantics associated with the
operation that are the same each time. This should ease review, maintenance and
understanding of the code.

The perfect shuffle splits the input vector into NUM_GROUPS groups and then
each group in WORDS_PER_GROUP. The output vector consists of
WORDS_PER_GROUP groups and each group has NUM_GROUPS words. The data is
remapped, so that the i-th word of the j-th word in the output vector is
the j-th word of the i-th group of the input vector.

The inverse operation of the perfect shuffle is the perfect shuffle with
both parameters swapped.
I.e. [perfect_suffle B A [perfect_shuffle A B data]] == data

Examples:
  NUM_GROUPS = 2, WORDS_PER_GROUP = 4
    [A B C D a b c d] => [A a B b C c D d]
  NUM_GROUPS = 4, WORDS_PER_GROUP = 2
    [A a B b C c D d] => [A B C D a b c d]
  NUM_GROUPS = 3, WORDS_PER_GROUP = 2
    [A B a b 1 2] => [A a 1 B b 2]

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-15 15:34:31 +03:00
Istvan Csomortani e7ea5dfa11 util_dacfifo: Align the dac_xfer_out to the first valid data 2018-10-11 16:57:30 +03:00
Istvan Csomortani a088a92364 util_dacfifo: Update the dma_ready generation
The write logic (DMA side) has to be independent from the read logic (DAC side).
In general the FIFO is always ready for the DMA, and every DMA transaction will
interrupt the read-back process, and the module will stop sending data,
until the initialization is finished.

Bringing back the write address tot he DMA clock domain is totally
redundant, so delete it.
2018-10-11 16:57:30 +03:00
Istvan Csomortani d2939f2a44 util_dacfifo: Simplify the write into buffer validation 2018-10-11 16:57:30 +03:00
Istvan Csomortani fa32ea8f1f util_dacfifo: Fix the reset logic of the module
Both the DMA and DAC side should be in reset at the positive edge of the
dma_xfer_req, so we can re-initialize the buffer.
2018-10-11 16:57:30 +03:00
Istvan Csomortani 6044aa3956 util_dacfifo: Update the bypass logic 2018-10-11 16:57:30 +03:00
Istvan Csomortani 6be4658d49 util_dacfifo_bypass: The FIFO in this module is for CDC only, no need to have a large depth 2018-10-11 16:57:30 +03:00
Istvan Csomortani 5b5218250b axi_dacfifo: Move util_dacfifo_bypass module to util_dacfifo IP 2018-10-11 16:57:30 +03:00
AndreiGrozav f8d38c9149 axi_ad6676: Support multiple lane configuration
Propagate parameter to tpl core.
2018-10-05 15:19:17 +03:00
AndreiGrozav 2756c153b7 axi_ad6676: Cosmetic update only 2018-10-04 16:08:31 +01:00
AndreiGrozav de725b8294 axi_ad6676: Support multiple lane configuration
-expose jesd lane nr parameter
2018-10-04 16:06:19 +01:00
Istvan Csomortani 42127c07fc util_adxcvr: Expose QPLL and CPLL *_CFG attributes 2018-10-04 14:37:02 +03:00
Istvan Csomortani 740715c6b3 util_adxcvr: Update GHTE4 input port from the wizard 2018-10-04 14:37:02 +03:00
Istvan Csomortani 0d3e05b311 axi|util_adxcvr: Expose TX configurable driver ports
Expose the TX configurable driver ports, more specifically the
TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This
provides a soft tunning capability of the transmit side of the
transceivers, in cases where the insertion loss of the channel is too
high or low, comparing to the default value supported by the default
configuration of the GTs.

You can find information about these configuration ports under the
section called 'TX Configurable Driver' in the GT transceivers user
guide. (UG476, UG576)
2018-10-04 14:37:02 +03:00
Istvan Csomortani 2602f239fa interfaces_ip.tcl: Delete trailing white spaces 2018-10-04 14:37:02 +03:00
Istvan Csomortani 8fc6ee8851 util_adxcvr: Define all GTHE4 attribute in binary
This commit does not contain any functional modification.

Because the wizard generates the attributes in binary, we should use
binary mode too, so we can compare different configurations more easily.
2018-10-04 14:37:02 +03:00
Istvan Csomortani e31cfe5639 util_adxcvr_xch: GTHE4 connect CPLL_FBDIV_45 attribute 2018-10-04 14:37:02 +03:00
Istvan Csomortani 99a1768813 Revert "util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate"
This reverts commit 9a74a40c49.
2018-10-04 14:37:02 +03:00
AndreiGrozav d865635bc7 axi_hdmi_tx: Associate vdma_clk to s_axis interface 2018-09-27 17:23:17 +03:00
AndreiGrozav c7d9fe56fd axi_hdmi_tx: Create s_axis interface 2018-09-27 11:45:28 +03:00
Laszlo Nagy db25ee1877 axi_dmac: fix transfer start synchronization
This change will fix the transfer start synchronization mechanism used
in the AXIS streaming and FIFO source interfaces.
2018-09-11 17:01:58 +03:00
Adrian Costina b01cf35cf7 axi_adcfifo: Fix constraints to apply also to Ultrascale devices
Used IS_SEQUENTIAL instead of PRIMITIVE_SUBGROUP==flop to identify ff related constraints
2018-09-07 17:44:47 +03:00
Laszlo Nagy 9d6f3de448 axi_dmac: assert xfer_request only when ready
If the req_valid asserts faster than the ID gets synchronized over we
assert the xfer request without being ready to accept data.
This can lead to overflow assertion when using a FIFO like interface.
2018-09-07 11:38:04 +03:00
Laszlo Nagy 20ac7dcaef axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
Laszlo Nagy a4c4e384bb axi_dmac: early abort 2d support 2018-09-07 11:38:04 +03:00
Laszlo Nagy a1cc20e3b9 axi_dmac: early abort support
Data mover/ src axis changes
  Request rewind ID if TLAST received during non-last burst
  Consume (ignore) descriptors until last segment received
  Block descriptors towards destination until last segment received

Request generator changes
  Rewind the burst ID if rewind request received
  Consume (ignore) descriptors until last segment received
  If TLAST happened on last segment replay next transfer (in progress or
   completed) with the adjusted ID
  Create completion requests for ignored segments

Response generator changes
  Track requests
  Complete segments which got ignored
2018-09-07 11:38:04 +03:00
Laszlo Nagy 2f3a95971c axi_dmac: request generator reworked to use FSM 2018-09-07 11:38:04 +03:00
Laszlo Nagy eb40b42c88 axi_dmac: preparation work for reporting length of partial transfers
Length of partial transfers are stored in a queue for SW reads.
The presence of partial transfer is indicated by a status bit.

The reporting can be enabled by a control bit.

The progress of any transfer can be followed by a debug register.
2018-09-07 11:38:04 +03:00
Laszlo Nagy 0203cd6981 axi_dmac: drive destination eot from source side 2018-09-07 11:38:04 +03:00
Laszlo Nagy 681b619fff axi_dmac: wire destination descriptor through source
Drive the descriptor from the source side to destination
so we can abort consecutive transfers in case TLAST asserts.

For AXIS count the length of the burst and pass that value to the
destination instead the programmed one. This is useful when the
streams aborts early by asserting the TLAST. We want to notify the
destination with the right number of beats received.

For FIFO source interface reuse the same logic due the small footprint
even if the stream does not got interrupted in that case.
For MM source interface wire the burst length from the request side to
destination.
2018-09-07 11:38:04 +03:00
Lars-Peter Clausen cf05286b2a axi_jesd204_tx: Fix multi-link constraints
The constraint for the synchronizer that synchronizes the sync_status
signal of the link only works correctly for the first link. For other links
no timing exception is applied, which leads to timing failures.

Fix this by using a wildcard constraint for the synchronizer reg number.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-28 15:38:49 +02:00
Lars-Peter Clausen f98c9e439b ad_dds_2: Don't try to round if signal is not truncated
If DDS_DW is equal to DDS_D_DW there is no signal truncation and
consequentially no rounding should be performed. But the check whether
rounding should be performed currently is for if DDS_DW is less or equal to
DDS_D_DW.

When both are equal C_T_WIDTH is 0. This results in the expression
'{(C_T_WIDTH){dds_data_int[DDS_D_DW-1]}};' being a 0 width signal. This is
not legal Verilog, but both the Intel and Xilinx tools seem to accept it
nevertheless.

But the iverilog simulation tools generates the following error:

	ad_dds_2.v:102: error: Concatenation repeat may not be zero in this context.

Xilinx Vivado also generates the following warning:

	WARNING: [Synth 8-693] zero replication count - replication ignored [ad_dds_2.v:102]

Change the condition so that truncation is only performed when DDS_DW is
less than DDS_D_DW. This fixes both the error and the warning.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-28 10:08:22 +02:00
Lars-Peter Clausen 396fb183f6 adi_ip_alt: ad_ip_create: Use 'description' for the DISPLAY_NAME propery
The DISPLAY_NAME of a module is supposed to be a short human readable
description of the IP core.

Currently this is set to the name of the IP, which already has its own
property called NAME.

This causes Platform Designer to display the descriptive labels if the IP
core basically as "$ip_core_name ($ip_core_name)".

The value that all current user of ad_ip_create pass for the description
parameter matches this criteria (And not so much the requirements for the
actual DESCRIPTION property).

Change things, so that the DISPLAY_NAME property is set to what is
currently passed as the description parameter.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-27 11:53:50 +02:00
Istvan Csomortani af5c71a9b2 axi|util_adxcvr: Delete reset interface inference for PLL resets
The Xilinx's reset interface expect that every reset have an associated
interface and clock signal. The tool will try to find its clock and interface,
and automatically associated clock signal to it.

The PLL resets are individual asynchronous resets. To simplify the design
and avoid invalid critical warnings all the reset interface inference
for the PLL resets were removed.
2018-08-23 18:41:48 +03:00
Istvan Csomortani dd0d9a1392 util_gmii_to_rgmii: Fix ip.tcl script
The property 'name' for GMII interface is automatically defined by the tool
as 'gmii'.

Delete the manual definition.
2018-08-23 18:41:48 +03:00