zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
5,996 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

5996 Commits (076e81a17c92b32040786e252a70e7e864f47689)

Author SHA1 Message Date
LIacob106 076e81a17c library: Add link to wiki for IPs 2021-10-25 10:44:53 +03:00
Istvan Csomortani 15a6480601 ad4630_fmc: Initial commit 2021-10-18 16:13:31 +03:00
Istvan Csomortani 6a526f4bb6 ad463x_data_capture: Initial commit 
IP required to support echo and master clock mode
 2021-10-18 16:13:31 +03:00
Istvan Csomortani 5ac64b021f spi_engine_execution: Delete control loop-back in sdi_data_valid generation 2021-10-18 16:13:31 +03:00
sergiu arpadi 6570c23a76 axi_spi_engine: Add generic config params 
The 4 parameters are added to facilitate transmiting project
related information to the software. They act as read-only
memory which is written in Vivado when the project builds.
Set 31 to SDI FIFO's almost full threshold
 2021-10-18 16:13:31 +03:00
Istvan Csomortani f86ae28e50 spi_engine/data_reorder: Initial commit 
In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.

The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
 2021-10-18 16:13:31 +03:00
Istvan Csomortani 6565c5d018 library/tb: Improve run_tb.sh 2021-10-18 16:13:31 +03:00
Mihaita Nagy ff090b60ef daq2/zcu102: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Mihaita Nagy 3640c2b584 daq2/kcu105: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Mihaita Nagy 6ad54c1056 daq2/kc705: Fix the ad9144 data offload to use internal bram 2021-10-15 15:03:22 +03:00
Mihaita Nagy 907cd613aa daq2/zc706: Increase BRAM utilization to 52% 2021-10-15 15:03:22 +03:00
LIacob106 e34346360d scripts: Add logic for vivado version check 2021-10-12 14:34:11 +03:00
Laszlo Nagy 812baf9022 Revert "data_offload: Fix timing violation" 
This reverts commit 1fe0d5f8e0.
 2021-10-08 11:42:05 +03:00
Laszlo Nagy 5db7574dce scripts/adi_board.tcl: For older families stick with axi_interconnect 
SmartConnect has higher resource utilization and worse timing closure
that makes several zed based projects to fail timing.
 2021-10-07 14:18:49 +03:00
Filip Gherman dbd5ffe4ed jesd204_rx: fixed makefile 2021-10-07 12:48:08 +03:00
Laszlo Nagy 0c6c28ed84 jesd204/ad_ip_jesd204_tpl : Add support for 12 lanes 2021-10-06 15:49:56 +03:00
Filip Gherman 9295218a64 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Laszlo Nagy 22e1366bfc jesd204/jesd204_rx: Define tie off values for unused ports 2021-10-05 14:09:51 +03:00
Laszlo Nagy aa93c17cdc jesd204/jesd204_tx/jesd204_tx.v: Have FFs initial value, useful for simulation 2021-10-05 14:09:51 +03:00
Laszlo Nagy 3a1babe366 ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock 
Reset transceiver with a pulse
 2021-10-05 14:09:51 +03:00
Laszlo Nagy 2562aead32 ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock 2021-10-05 14:09:51 +03:00
Laszlo Nagy 8d547f31e1 ad9081_fmca_ebz/vck190: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 6c58a8d1ab ad9081_fmca_ebz/common: Add Versal transceiver support 2021-10-05 14:09:51 +03:00
Laszlo Nagy 1a9e7dbeb4 jesd204:jesd204_versal_gt_adapter_rx/tx: Add adapter for Versal transceiver IP 2021-10-05 14:09:51 +03:00
Laszlo Nagy 56a25afa68 common/vck190: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 6a681b9e8d common/vmk180_es1: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 833e5f0aff common/vmk180: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 2fec1356d6 scripts/adi_project_xilinx.tcl: VCK190 support 2021-10-05 14:09:51 +03:00
Laszlo Nagy 222c5782b6 scripts/adi_project_xilinx.tcl: Install ES1 board from XHUB, make project compile in batch mode 2021-10-05 14:09:51 +03:00
Laszlo Nagy 011c8c1f36 scripts/adi_project_xilinx.tcl: Add VMK180 & VMK180_ES1 support 2021-10-05 14:09:51 +03:00
Laszlo Nagy c22f622599 scripts/adi_board.tcl: Versal support for memory interconnect and irq interconnect 2021-10-05 14:09:51 +03:00
Laszlo Nagy 4d12c4d99a scripts/adi_xilinx_device_info_enc.tcl: Add Versal support 2021-10-05 14:09:51 +03:00
Laszlo Nagy 2b242bf06f scripts/adi_ip_xilinx.tcl: Enable auto family support 
Some IPs like JESD link layer were marked as not supported on Versal devices by
the current flow while other not (e.g. TPL).
The auto family support seems to workaround this issue.
 2021-10-05 14:09:51 +03:00
Laszlo Nagy 08c2ce75fe scripts/adi_board.tcl: Switch cpu_interconnect to SmartConnect 2021-10-05 14:09:51 +03:00
Laszlo Nagy aaaba50f83 scripts/project-xilinx.mk: Update target to xsa and cleanup list 2021-10-05 14:09:51 +03:00
Laszlo Nagy 57546b853d .gitignore: Ignore Versal files 2021-10-05 14:09:51 +03:00
Laszlo Nagy d94ec80e08 Update README.md 
Correct the  ZCU102 PL DDR memory controller interface width and speed based on available options of the MIG
 2021-10-05 11:59:51 +03:00
LIacob106 0a986f76b8 scripts: QUARTUS_VERSION and PRO_ISUSED can be set in system_project.tcl 2021-10-02 12:34:10 +03:00
Adrian Costina 0a3724e04c s10soc: Update base desgin from ES to production, H-Tile version 2021-09-30 17:40:13 +03:00
Istvan Csomortani 5a3c3c878b ad9213_dual_ebz: Initial commit 
Used ADF4377 SPI configuration CPOL/CPHA 1 for increasing the reliability of the level translators
ad9213_dual_ebz/s10soc: Redesign the address layout

avl_peripheral_mm_bridge 0x0000000 0x0001FFFF
  * sys_gpio_in  0x00000000
  * sys_gpio_out 0x00000020
  * sys_spi      0x00000040
  * sys_gpio_bd  0x000000D0
  * sys_id       0x000000E0

avl_mm_bridge_0 0x00040000 0x0007FFFF
  * ad9213_rx_0.phy_reconfig_0     0x00000000
  * ad9213_rx_0.phy_reconfig_1     0x00002000
  * ad9213_rx_0.phy_reconfig_2     0x00004000
  * ad9213_rx_0.phy_reconfig_3     0x00006000
  * ad9213_rx_0.phy_reconfig_4     0x00008000
  * ad9213_rx_0.phy_reconfig_5     0x0000A000
  * ad9213_rx_0.phy_reconfig_6     0x0000C000
  * ad9213_rx_0.phy_reconfig_7     0x0000E000
  * ad9213_rx_0.phy_reconfig_8     0x00010000
  * ad9213_rx_0.phy_reconfig_9     0x00012000
  * ad9213_rx_0.phy_reconfig_10    0x00014000
  * ad9213_rx_0.phy_reconfig_11    0x00016000
  * ad9213_rx_0.phy_reconfig_12    0x00018000
  * ad9213_rx_0.phy_reconfig_13    0x0001A000
  * ad9213_rx_0.phy_reconfig_14    0x0001C000
  * ad9213_rx_0.phy_reconfig_15    0x0001E000
  * ad9213_rx_0.link_pll_reconfig  0x00020000

avl_mm_bridge_1 0x00080000 0x000BFFFF
  * ad9213_rx_1.phy_reconfig_0     0x00000000
  * ad9213_rx_1.phy_reconfig_1     0x00002000
  * ad9213_rx_1.phy_reconfig_2     0x00004000
  * ad9213_rx_1.phy_reconfig_3     0x00006000
  * ad9213_rx_1.phy_reconfig_4     0x00008000
  * ad9213_rx_1.phy_reconfig_5     0x0000A000
  * ad9213_rx_1.phy_reconfig_6     0x0000C000
  * ad9213_rx_1.phy_reconfig_7     0x0000E000
  * ad9213_rx_1.phy_reconfig_8     0x00010000
  * ad9213_rx_1.phy_reconfig_9     0x00012000
  * ad9213_rx_1.phy_reconfig_10    0x00014000
  * ad9213_rx_1.phy_reconfig_11    0x00016000
  * ad9213_rx_1.phy_reconfig_12    0x00018000
  * ad9213_rx_1.phy_reconfig_13    0x0001A000
  * ad9213_rx_1.phy_reconfig_14    0x0001C000
  * ad9213_rx_1.phy_reconfig_15    0x0001E000
  * ad9213_rx_1.link_pll_reconfig  0x00020000

Connected directly to the h2s_lw_axi_master
  * ad9213_rx_0.link_reconfig      0x000C0000
  * ad9213_rx_0.link_management    0x000C4000
  * ad9213_rx_1.link_reconfig      0x000C8000
  * ad9213_rx_1.link_management    0x000CC000
  * axi_ad9213_0.s_axi             0x000D0000
  * axi_ad9213_1.s_axi             0x000D1000
  * axi_ad9213_dma_0.s_axi         0x000D2000
  * axi_ad9213_dma_1.s_axi         0x000D3800
 2021-09-30 17:40:13 +03:00
Istvan Csomortani 8acf0296af s10soc:ad_cpu_interconnect: Add an avl_address_width attribute 
The default address space for a new bridge is 256 Kbytes. Add an
avl_address_width attribute to the ad_cpu_interoconnect porecess to
define other address space sizes if needed.

The avl_peripheral_mm_bridge will have an 128 Kbyte address space from
address 0x0000.
 2021-09-30 17:40:13 +03:00
David Winter edd2956d58 data_offload: Fix util_[cu]pack offset to TDD syncs 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-30 14:45:54 +03:00
David Winter b9554a9a5a ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-30 14:45:54 +03:00
stefan.raus 58737e09ba adi_project_intel.tcl: update quartus to 21.2 
Update Quartus version to 21.2.0.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
 2021-09-30 09:53:53 +03:00
David Winter 0e8f55b2d7 data_offload: Fix oversized inputs in TX mode 
This commit fixes an issue in situations where we provide an oversized
transaction to the data offload in TX mode. Previously, the data offload
would stop accepting new data (wr_ready <= 0) after filling up the
internal storage, and get stuck waiting for the input transaction to
end, thus locking up the device.

This commit addresses that issue by allowing the data offload to consume
the full input transaction, even if the tail of the buffer will be
truncated in the output.

Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-29 18:33:11 +03:00
Filip Gherman 7ed4955661 axi_adxcvr_ip.tcl util_adxcvr_ip.tcl: Fixed asynchronous resets critical warnings in XCVR 2021-09-28 04:53:02 +03:00
stefan.raus cfe0c0ced5 adi_project_xilinx.tcl, adi_ip_xilinx.tcl: update version to 2021.1 
Update vivado version from 2020.2 to 2021.1 in projects and library scripts.
 2021-09-24 12:11:11 +03:00
Mihaita Nagy 1fe0d5f8e0 data_offload: Fix timing violation 2021-09-22 12:18:33 +03:00
David Winter cdb9a0af2b data_offload: Add sync to cyclic mode 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-21 09:06:03 +03:00