Commit Graph

86 Commits (075ee05189cb285d66a35496c7eb9b044c380b11)

Author SHA1 Message Date
Iulia Moldovan db94628cc6 library & projects: Update Makefiles
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters.
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Robin Getz 63b6711cfa start adding some doc to the ./projects directory
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
2021-11-10 14:01:06 +02:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Istvan Csomortani d9639db991 m2k: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
AndreiGrozav 912e09ad18 m2k: Add DAC last sample connections 2020-11-02 15:50:12 +02:00
AndreiGrozav 0152b645a6 m2k: Fix Warnings
Fix warnings caused by attempting to set a value to a disabled parameter.
2020-09-11 10:23:26 +03:00
AndreiGrozav 4766d01915 m2k: Update constraints 2020-08-13 07:01:19 +03:00
AndreiGrozav 4d39a3595f m2k: Connect signals for instrument sync 2020-08-13 07:01:19 +03:00
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
AndreiGrozav e1353d5291 m2k: use DMA streaming interface
The previous mechanism was "probing" the DMAs for valid data. Better said,
each interpolation channel enabled it's DMA until a valid data was received,
then it disabled the DMA read and waited for the adjacent channel(DMA) to
receive a valid data. Only when for both channels had valid data on the
DMAs interfaces was the transmission started. This added an undesired and
redundant complexity to the interpolation channels. Furthermore, for continuous
transmission, using the above mechanism lead to a fixed phase(sample)
shift between the two channels at each start.

By using the streaming mechanism the interface is simplified and the
above problems are solved.
2020-03-06 15:57:43 +02:00
AndreiGrozav 8131c86f75 m2k: Connect the adc_trigger reset 2019-11-25 13:14:18 +00:00
AndreiGrozav 514aadb54e m2k: Use dac trigger 2019-11-15 12:23:01 +00:00
AndreiGrozav 9323f4193c m2k: Clean old interrupt connection style 2019-10-18 18:28:01 +03:00
AndreiGrozav 9f112640f3 m2k: Change constraint to match the new LA path 2019-09-13 11:55:11 +03:00
AndreiGrozav e7cca7c5f7 m2k: Update for axi_dac_interpolate start sync 2019-08-22 18:07:45 +03:00
AndreiGrozav 6f540b0ef2 m2k: Add cascading support
-remove util_extract
-instrument triggering logic_analyzer <-> adc_trigger using dedicated latency paths
-move logic_analyzer on adc clock domain (100MHz -> 100MHz)
2019-08-22 18:06:10 +03:00
Laszlo Nagy 0261eade0c zynq:all: fix SPI clock constraint
According to data sheets the EMIO SPI controller maximum frequency is
just 25MHz. Constrain the SPI clock accordingly.
2019-08-09 16:39:56 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
AndreiGrozav 0a3a99bf83 m2k: Define SPI clock constraint 2019-06-21 09:53:14 +03:00
Adrian Costina d80692da03 m2k: Remove memory interconnects and connect directly to the HP ports
Vivado generates errors with the smartconnect change, altough the interconnect should be synthesized out
2019-04-15 17:49:11 +03:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Adrian Costina 86748825d0 m2k: Downgrade SPI related critical warning, as we use lower clock speed for power reasons 2018-08-23 18:41:48 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Adrian Costina 6e7b19c944 Remove projects we don't support anymore 2018-06-15 16:17:48 +03:00
Lars-Peter Clausen b20714bae2 Regenerate project top-level Makefiles
Removes a lot of boilerplate code.

Using the new scheme it is possible to add new projects or sub-projects
without having to re-generate any existing Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 377247a434 Regenerate project Makefiles using the new shared Makefile includes
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Adrian Costina 98b58562d6 system_top: Non functional changes in system_tops to reduce warnings
Loop back the unused GPIO pins, and add all the SPI interface to system
wrapper instance.

The following system_top modules were changed:
  - ad738x_fmc
  - ad7616_sdz
  - ad77681evb
  - ad77681evb
  - ad7768evb
  - ad9739a_fmc
  - ad9434
  - adrv9739
  - fmcadc5
  - ad6676evb
  - ad9265
  - ad5766
  - fmcomms5
  - m2k
2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
Adrian Costina cb2fd6af73 dm2k: Drive the ADC DMA valid from the trigger extracting core 2017-08-30 18:28:52 +03:00
Adrian Costina 5c252783e7 m2k: Move ADC hardware gain correction from the AD9963 IP to AXI_ADC_DECIMATE IP 2017-08-04 14:29:27 +03:00
Adrian Costina 83c1e555b1 m2k: Enable correction for the interpolation module 2017-08-03 17:24:26 +03:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Adrian Costina 0d99aa02e1 m2k: Updated project to work with the fifo_depth related changes 2017-06-06 15:37:23 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 414943db4b m2k: Fix Make files 2017-05-26 09:54:08 +03:00
Istvan Csomortani 4c998d1e18 make: Update make files 2017-05-25 15:12:17 +03:00
Adrian Costina f9057b1825 m2k: Add scale correction option. Update parameters 2017-05-24 15:59:24 +03:00
Lars-Peter Clausen e033d6c48e m2k: Refresh Makefile
The util_cpack core is currently not used by the M2K project. Refresh the
Makefiles to reflect this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-19 15:33:26 +02:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty cfd4e006b3 hdlmake updates 2017-04-25 15:46:26 -04:00
Adrian Costina a6457cb54f m2k:standalone, remove power optimizations as they are performed manually
- testing shows that the actual power consumtion is a bit less with them turned off
2017-04-25 10:09:55 +03:00
Lars-Peter Clausen 6d72ce800c m2k: zed: Fix default HDMI clock frequency
The input clock frequency of the axi_clkgen was changed from 200 MHz to
100 Mhz. Update the divider settings accordingly to keep the standard
default output frequency of 148.5 MHz.

The incorrect divider settings did not affect operation of the design since
software reprograms them at startup anyway, but changing them avoids the
following warning:
	[DRC 23-20] Rule violation (AVAL-46) v7v8_mmcm_fvco_rule1 - The current computed target frequency, FVCO, is out of range for cell i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm. The computed FVCO is 445.455 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 49.000, CLKIN1_PERIOD = 10.00000, and DIVCLK_DIVIDE = 11 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)).
	This violation may be corrected by:
	  1. The timer uses timing constraints for clock period or clock frequency that affect CLKIN1 to set cell attribute CLKIN1_PERIOD, over-riding any previous value. This may already be in place and, if so this violation will be resolved once Timing is run.  Otherwise, consider modifying timing constraints to adjust the CLKIN1_PERIOD and bring FVCO into the allowed range.
	  2. In the absence of timing constraints that affect CLKIN1, consider modifying the cell CLKIN1_PERIOD to bring FVCO into the allowed range.
	  3. If CLKIN1_PERIOD is satisfactory, modify the CLKFBOUT_MULT_F or DIVCLK_DIVIDE cell attributes to bring FVCO into the allowed range.
	  4. The MMCM configuration may be dynamically modified by use of DRP which is recognized by an ACTIVE signal on DCLK pin.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 20:36:34 +02:00
Lars-Peter Clausen 0ffbe50163 m2k: zed: Run video DMA at higher clock rate
For the M2K standalone version we run the interface clock at a lower rate
to reduce the power consumption. While this is not necessary on the ZED
board we also run the interface at a lower rate for consistency.

Currently the video DMA on the ZED board uses the interface clock for the
data path as well. This is now too slow to support 1080p@60Hz so move it
over to a faster clock.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 16:29:09 +02:00