Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Fix CONVERTER_RESOLUTION parameter setting for ad9250. Also deleted the
setting of BITS_PER_SAMPLE and DMA_BITS_PER_SAMPLE for ad9250 since they
are set by default to the desired values.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Modified the project such that there is only one data path for the ADC data: deleted one of the JESD tpl instances, one of the cpack instances and one of the dma instances.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The script specifies the OUT_CLK_SEL and SYS_CLK_SEL parameter values as
binary numbers. But the tools will interpret them as decimal number
resulting in the wrong selection for OUT_CLK_SEL. Specify the parameter
values as decimal values to avoid this.
This is not a critical issue since software will overwrite this setting at
system boot-up. But it should be fixed anyway.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.
Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Convert the FMCJESDADC1 project to the ADI JESD204 link layer core. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
If a parameter value is defined as a string binary (e.g. "001001000000"),
it can confuse the tool, and the value may be used as a decimal number.
To prevent this issue and to improve readability converting all the binary
constants into hexadecimal.
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
AndrDragomir
Iulia Moldovan
PopPaul2021
Dan Hotoleanu
Laszlo Nagy
hotoleanudan
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina
Rejeesh Kutty
AndreiGrozav