pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Iulia Moldovan	961ebe0cc2	projects: Update .v files according to guideline Deleted lines after endmodule and consecutive empty lines. Modified parentheses, extra spaces. Fixed indentation. Fixed parameters list to be each parameter on its line. Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>	2022-06-28 18:06:56 +03:00
hotoleanudan	1c208c01d6	ad9656:Add reference design for the ad9656 eval board (#494 ) Added reference design for the ad9656 evaluation board coupled with the zcu102 carrier board. The JESD204 communication link that transfers data from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1, F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>	2020-10-06 09:53:40 +03:00

Author

SHA1

Message

Date

Iulia Moldovan

961ebe0cc2

projects: Update .v files according to guideline

Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>

2022-06-28 18:06:56 +03:00

hotoleanudan

1c208c01d6

ad9656:Add reference design for the ad9656 eval board (#494 )

Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>

2020-10-06 09:53:40 +03:00

2 Commits (075ee05189cb285d66a35496c7eb9b044c380b11)