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Author SHA1 Message Date
AndrDragomir 72378a6d4a projects: Add fmc connection files for eval boards 
Creating a new eval board fmc file:
  - docs: Open FMC_eval_board_template.xlsx
  - follow the instructions on the first sheet
 2022-09-20 14:11:08 +03:00
Laszlo Nagy dafdd1c1e9 ad9208_dual_ebz: Use ad_xcvrcon procedure to connect device clock 2021-02-05 15:24:15 +02:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 2019-06-11 18:13:06 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
Laszlo Nagy 607f2bd8de ad9208_dual_ebz: Initial version 
This commit add support for the dual AD9208-DUAL-EBZ board.

The clocking scheme is different from the other projects.
The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK),
it is received directly from the clockchip  SCLKOUT9 output through the REFCLK1.
This is needed for deterministic latency where SYSREF must be sampled
with the device clock by meeting setup and hold time.

The two channels from each converter are merged together and transferred  to the DDR with a single DMA.

It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL.

REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC
board.
 2019-05-16 13:29:34 +03:00