Rejeesh Kutty
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8761db438e
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axi_fifo2f: common interface with fifo2s
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2014-11-12 15:15:32 -05:00 |
|
Rejeesh Kutty
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925e966eb6
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axi_fifo2s: fifo full replaced with ready
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2014-11-12 14:43:47 -05:00 |
|
Rejeesh Kutty
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5fc4f1b000
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axi_fifo2s: buswidth fix
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2014-11-12 14:43:46 -05:00 |
|
Rejeesh Kutty
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d204a7c2b7
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:44 -05:00 |
|
Rejeesh Kutty
|
e7cec7171e
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:43 -05:00 |
|
Rejeesh Kutty
|
4381f20a6a
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:42 -05:00 |
|
Rejeesh Kutty
|
9f2dbad539
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:41 -05:00 |
|
Rejeesh Kutty
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e683b5868e
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:40 -05:00 |
|
Rejeesh Kutty
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81b4cd532d
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:38 -05:00 |
|
Rejeesh Kutty
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888ab888d2
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:37 -05:00 |
Istvan Csomortani
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f8e7796592
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axi_jesd_gt: Fix lane number parameters
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2014-11-12 17:43:32 +02:00 |
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Istvan Csomortani
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bf62665c56
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prcfg_qpsk: Add Simulink model
Matlab version used: R2014a, HDL Coder 3.3
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2014-11-12 15:44:38 +02:00 |
|
Rejeesh Kutty
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64ec633438
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gt: asymmetric no of lanes
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2014-11-11 08:54:24 -05:00 |
|
Rejeesh Kutty
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cb15567a56
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ad6676: added
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2014-11-10 13:36:07 -05:00 |
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Istvan Csomortani
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c6df568a00
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Revert "ad_interrupts: Initial check in."
This reverts commit b254380338.
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2014-11-06 12:16:52 +02:00 |
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Rejeesh Kutty
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b11d80ed98
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ad_rst: changed to dual stage
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2014-11-05 16:48:02 -05:00 |
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Rejeesh Kutty
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74ec396b27
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ad_rst: ultrascale -dual stage
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2014-11-05 16:47:41 -05:00 |
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Rejeesh Kutty
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d69ccebbde
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ad9234: full 16bit samples
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2014-11-05 11:59:08 -05:00 |
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Rejeesh Kutty
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403fe1b373
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wfifo: read only if ready is asserted
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2014-10-31 13:05:17 -04:00 |
Adrian Costina
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38652b1c3e
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axi_ad9643: Added constraint file
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2014-10-31 17:57:47 +02:00 |
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Adrian Costina
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3e9ce71d21
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axi_ad9122: Added constraint file
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2014-10-31 17:56:56 +02:00 |
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Istvan Csomortani
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d596d71285
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prcfg_qpsk: Swap the I/Q pair nets between the filter and the demodulator.
This fix the wrong symbol mapping issue.
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2014-10-31 12:14:52 +02:00 |
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Istvan Csomortani
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eb520b1f75
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prcfg_qpsk: Major update
Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.
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2014-10-31 12:10:59 +02:00 |
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Istvan Csomortani
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ea194755e1
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prcfg: Upgrade the QPSK logic
Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
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2014-10-31 11:59:29 +02:00 |
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Rejeesh Kutty
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9818bcb601
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axi_fifo2f: internal memory low overhead
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2014-10-30 11:12:10 -04:00 |
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Rejeesh Kutty
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17cb1d9585
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common/mem: asymmetric version
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2014-10-30 11:12:09 -04:00 |
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Rejeesh Kutty
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6470ea91ad
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axi_fifo2f: fake version
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2014-10-30 11:12:08 -04:00 |
Lars-Peter Clausen
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f9628262aa
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axi_dmac: Add xfer_req signal to the streamin AXI source interface
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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2014-10-29 18:15:54 +01:00 |
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Adrian Costina
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fbce64411e
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axi_ad9671: added synchronization interface to altera core
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2014-10-29 18:20:26 +02:00 |
acozma
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36c7034bd6
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ad7175: Fix dma issues
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2014-10-28 16:00:06 +02:00 |
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acozma
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9c8fe5f09c
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ad7175: Removed unused files
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2014-10-28 14:30:41 +02:00 |
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acozma
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9e1d1c1b49
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ad7175: Updated the AD7175 IP and project
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2014-10-28 14:28:38 +02:00 |
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Istvan Csomortani
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b254380338
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ad_interrupts: Initial check in.
Initial check in of the interrupt concatenation block.
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2014-10-27 19:34:34 +02:00 |
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Adrian Costina
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e086f5eb9f
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axi_ad9361: Updated core with the new up_adc_common register set
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2014-10-27 19:26:40 +02:00 |
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Rejeesh Kutty
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7e52cf9568
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up_axi: timeout generating multiple/repeated acks
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2014-10-23 13:51:33 -04:00 |
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Istvan Csomortani
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3dbfa8cda6
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ad9434_fmc: Fix PN monitor and device interrupt
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2014-10-23 11:29:14 +03:00 |
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acozma
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b9ca616150
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Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
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2014-10-23 06:11:52 +03:00 |
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acozma
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da8454ae4c
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axi_ad7175: Added the AD7175 IP
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2014-10-23 06:11:41 +03:00 |
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Rejeesh Kutty
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6f723ef9e5
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axi_jesd_gt: lane mux on char qualifiers
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2014-10-22 15:29:25 -04:00 |
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Adrian Costina
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fe92b8b210
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axi_ad9671: Updated synchronization mechanism to have a software defined starting code
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2014-10-22 13:10:28 +03:00 |
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Adrian Costina
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121a416916
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axi_dmac: Fixed constraints for axi_dmac core
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2014-10-22 13:07:55 +03:00 |
|
Adrian Costina
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1d26639d73
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common: Added synchronization mechanism to the up_adc_common module
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2014-10-22 10:05:55 +03:00 |
|
Istvan Csomortani
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4b19646ed9
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ad9434_fmc: Fix samples order.
Four consecutive samples were reversed.
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2014-10-21 16:34:28 +03:00 |
|
Rejeesh Kutty
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46d1710539
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axi_ad9625: added constraints
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2014-10-17 13:57:30 -04:00 |
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Rejeesh Kutty
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37b608f397
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axi_ad9144: added constraints
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2014-10-17 13:57:09 -04:00 |
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Rejeesh Kutty
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df3915e2b0
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ad9625: constraints added
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2014-10-17 13:41:56 -04:00 |
|
Adrian Costina
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819a3d0802
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util_adc_pack: removed latches
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2014-10-17 15:40:16 +03:00 |
|
Rejeesh Kutty
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9d43a08865
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gt: constraint modifications
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2014-10-15 14:51:01 -04:00 |
|
Rejeesh Kutty
|
86724f7fc7
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gt: tx lane interleaving
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2014-10-15 14:51:00 -04:00 |
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Rejeesh Kutty
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206b96d55a
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ip: constraint changes
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2014-10-15 14:50:58 -04:00 |