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75 Commits (06b28d2e2429cc34baf0cdad0f02b13bc2e53e0d)

Author SHA1 Message Date
Rejeesh Kutty 06b28d2e24 ad9671: compile fixes 2014-04-11 14:28:22 -04:00
Rejeesh Kutty e92e6b2fd5 ad9671_fmc: changed for ad9671-fmc 2014-04-11 14:28:21 -04:00
Rejeesh Kutty 72e318a247 ad9671_fmc: initial checkin 2014-04-11 14:28:20 -04:00
ATofan 99ef34936f Merge branch 'master' of https://github.com/analogdevicesinc/hdl 2014-04-11 18:14:08 +03:00
Adrian Costina d0f04fd788 fmcomms1: Commit AC701 and VC707 projects 2014-04-11 17:35:25 +03:00
Istvan Csomortani c718169f27 adi_board.tcl : Fix the address assignment command 
A lot of cores have more than one address segments, therefor need
	to filter out the segment of the axi lite interface
 2014-04-11 16:14:56 +03:00
Istvan Csomortani cf5b9b51fd adi_board.tcl : Fix spi ports and hp clocks 2014-04-11 15:31:12 +03:00
Istvan Csomortani 37e2059fd0 adi_board.tcl : General update 
- Split the adi_dma_interconnect to two procedure:
	  adi_dma_interconnect and adi_hp_assign
	- Fix the adi_spi_core
	- Fix the adi_interconnect_lite
 2014-04-10 18:29:14 +03:00
Rejeesh Kutty 96541f0a7f usdrx1: zc706 updated for usdrx1 2014-04-10 11:05:13 -04:00
Rejeesh Kutty 6f36f74eea usdrx1: common board files 2014-04-10 11:05:11 -04:00
Rejeesh Kutty ac1c145a61 usdrx1: initial checkin 2014-04-10 11:05:10 -04:00
Lars-Peter Clausen dc7b3e085c axi_dmac: Fix issues with non 64-bit AXI masters 
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 14:54:22 +02:00
ATofan 9d19145713 Merge branch 'master' of https://github.com/analogdevicesinc/hdl 2014-04-10 10:50:53 +03:00
ATofan 5aac9d7288 FMCOMMS2 added sync option 
Added signals to allow synchronisation of multiple AD9361.
 2014-04-10 10:46:42 +03:00
Rejeesh Kutty fbfd658f0d zc706: added pl ddr3 mig 2014-04-09 15:58:12 -04:00
Istvan Csomortani e73952a694 ad9467 : initial checkin 2014-04-09 17:34:40 +03:00
Istvan Csomortani 5b0e37b97a adi_project.tcl : Modify implementation strategy 
- Change implementation strategy to Performance Explore.
	  At some projects, this could prevent timing issues, it not
	  increase the overall implementation time in a dramatic way.
 2014-04-07 15:02:38 +03:00
Rejeesh Kutty 33979fc533 fixes to improve timing - fifo for clock domain transfers 2014-04-04 13:49:53 -04:00
Rejeesh Kutty 6a19b34a00 a5gt: added tightly coupled memory 2014-04-03 20:50:17 -04:00
Rejeesh Kutty 04ab34c8ed a5gt: ethernet assignments 2014-04-03 20:50:16 -04:00
Rejeesh Kutty 12e5cc91bd make signaltap/timing part of the flow 2014-04-03 20:50:15 -04:00
Adrian Costina d0a8b4a63c kc705,common: Mem_interconnect maximize performance 
For FMCOMMS1, when both the ADC and DAC DMAs are active, the system was
unstable. With this fix, it the system seems to be stable.
 2014-04-03 15:59:33 +03:00
Rejeesh Kutty e85153b5dd altera hal version 2014-04-01 21:12:11 -04:00
Rejeesh Kutty 04df908fbf altera-fmcjesdadc1 initial checkin 2014-04-01 12:01:57 -04:00
Rejeesh Kutty 0d678b89ed altera a5gt fmcjesdadc1 setup 2014-04-01 11:46:37 -04:00
Istvan Csomortani 8deb36ce08 adi_board.tcl: All procedures works on Zynq/Microblaze 
General patch for the integration procedures. Tested on kc705 and
	zed.
 2014-04-01 16:19:24 +03:00
ATofan 9676146725 FMCOMMS2 AC701 Project 
Not tested - must program Vadj on board
 2014-04-01 15:35:44 +03:00
ATofan e597467447 FMCOMMS2 VC707 Project 2014-04-01 15:34:29 +03:00
ATofan 814b0d72d6 Modified Reset signals for FMCOMMS2 base design 
Made all resets the same (sys_100m_resetn)
 2014-04-01 15:32:48 +03:00
Istvan Csomortani fbafaa8507 MicroBlaze base system: Fix a few net names 
Every interconnect interface net name follows the convention:
	<interconnect name>_<interface name>
	No changes in logic or any connection!
 2014-04-01 10:40:35 +03:00
Adrian Costina f0b8b8f6c0 FMCOMMS1: KC705 updated system_top and constraints 
Needed to be compatible with the latest common file
 2014-03-31 17:49:10 +03:00
Adrian Costina 14b82c03dd FMCOMMS1: Several modifications in the base design 
Corrected the ADC/DAC interrupt location for microblaze systems
Removed the ILA clock generation from sys_audio_clkgen and created a
separate clock generator
All system is reset from the same source
 2014-03-31 17:44:57 +03:00
Adrian Costina a881557645 base_design: Fixed AC701 and VC707 contstraints 
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
 2014-03-31 17:38:20 +03:00
Istvan Csomortani 4ef88a3bed adi_board.tcl : Patch for adi_spi_core process 
- Fix indentation
	- Pacth for adi_spi_core process
 2014-03-31 16:41:07 +03:00
Istvan Csomortani 7f4f200fce Project scripts: Initial check in of adi_board.tcl 
The script contains integration tcl processes.
 2014-03-26 19:08:56 +02:00
Istvan Csomortani f9a67371c0 Zynq Base System: Reset is synchronized to lowest system clock 
System reset (sys_100m_reset) is synchronized to lowest system
	clock (FCLK0), via a Processor System Reset module
 2014-03-26 17:58:14 +02:00
Adrian Costina ad5ef35b48 fmcomms1: modified *_bd.tcl files formatting 2014-03-26 12:05:42 +02:00
Adrian Costina 8f7d4c9b26 FMCOMMS1: Fixed typo in common/fmcomms1_bd.tcl 2014-03-25 14:34:55 +02:00
Istvan Csomortani 0f10623be4 AC701/VC707: Define common variables 
Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
 2014-03-25 14:24:51 +02:00
Adrian Costina 2070c66b87 Fmcomms1: Initial commit for KC705 
Modified common project so it can be compatible for both ARM and
Microblaze based systems.
 2014-03-24 16:52:24 +02:00
Istvan Csomortani aa7b0bb4dd VC707 basesys: General fixes, actual status: working 
- Add an auxiliary cpu interconnect
	- Add an auxiliary interrupt concatenation module
	- Add new MIG file, current frequency of the DDR interface is 100
	  Mhz
	- Memory interconnect optimisation strategy is 'Maximize
	  Performance'
 2014-03-24 13:07:48 +02:00
Istvan Csomortani b94acf78aa AC701 bases sys: Add an auxiliary cpu interconnect 
- Add an auxiliary cpu interconnect, the KC705 base system was
	  used as reference
	- Base system is tested and working
 2014-03-24 13:01:52 +02:00
Istvan Csomortani 792e8a208d KC705 base system: Make a few cosmetic changes 2014-03-24 12:55:37 +02:00
ATofan f8c1179bc1 FMCOMMS2 KC705 Project. 
Added the files required for the FMCOMMS2 KC705 project.
Both DMA and DDS work.
 2014-03-24 11:48:52 +02:00
Istvan Csomortani 8a08031dce AC701: Modify interrupt concatenation 
- Interrupt concatenation is the same as in case of KC705
 2014-03-24 10:20:56 +02:00
Istvan Csomortani 13b4dd07d0 KC705 base system: Modify interrupt concatanation 
- Add an aditional interrupt input net for the sys_concat_aux_intc
	  module
 2014-03-21 14:45:18 +02:00
Istvan Csomortani c6143dbfaf KC705 base system: Delete trailing whitespaces. 2014-03-21 14:42:27 +02:00
ATofan 31a1ff384d FMCOMMS2 Base Design tcl modified 
Added support for both Zynq and MicroBlaze projects
 2014-03-21 09:57:52 +02:00
Istvan Csomortani 3a0d1282b7 Fix the remaining issues 
- Swap the IO locations of ports vsync and hsync
	- Change the mem_interconnect optimization strategy to Maximize
	  Performance
 2014-03-20 14:36:01 +02:00
Adrian Costina 698e9f4757 Added phys_opt_design step for fixing timing 
The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step
is part of the implmentation flow, with the Explore argument.
"This step performs physical optimizations such as timing-driven
replicaiton of high fanouts nets to improve timing results"
 2014-03-19 16:42:44 +02:00