Add support for querying the clock domains of the clock pins for the
axi_dmac controller. This allows the core to automatically figure out
whether its different parts run in different clock domains or not and setup
the configuration parameters accordingly.
Being able to auto-detect those configuration parameters makes the core
easier to use and also avoids accidental misconfiguration.
It is still possible to automatically overwrite the configuration
parameters by hand if necessary.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
bd files can be used to automate certain tasks in IP integrator when the
core is instantiated. Add a helper command for adding such files to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.
This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.
This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.
This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.
This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For some reason, if a core has an AXI and an AXI Stream interface too, the tool sets the AXI interface's ASSOCIATED_RESET parameter to the AXI Stream interface's reset.
This cause an unconnected AXI reset port in the block design. This 'set_property' command intended to overwrite this automated setup.
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
- removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core
- removed delay related xdc constraints as they are not needed
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the hdmi_de_int signal is asserted one clock cycle too early in
packed 422 mode. As a result the EAV sequence ends up in the first pixel
and every other pixel is off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check for both full range and limited range test-pattern sequences and only
if both don't match assert the tpm_oos signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Move the test pattern matcher to its own module. This makes it easier to
use it in other configurations as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the hdmi_de_int signal is asserted one clock cycle too early in
packed 422 mode. As a result the EAV sequence ends up in the first pixel
and every other pixel is off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check for both full range and limited range test-pattern sequences and only
if both don't match assert the tpm_oos signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Move the test pattern matcher to its own module. This makes it easier to
use it in other configurations as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
It also allows to configure the fixed delay value so that no additional constraints are needed
The default value of 18 seems to work very well(450mbps tx / 640 mbps rx) on the motor control platform used for tests
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
Lars-Peter Clausen
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
Paul Cercueil