Commit Graph

4959 Commits (04af519af87dcf293fb0bd14131738425a552c18)

Author SHA1 Message Date
AndreiGrozav 449911fd8f Remove adv7511/common: Deprecated
The common/adv7511_bd.tcl was used by projects based on microblaze
architectures, which are not supported anymore.
2018-08-16 10:05:02 +03:00
Istvan Csomortani bc692b9bd5 ad_rst: Synthesis attribute 'preserve' is redundant 2018-08-14 17:54:14 +03:00
Istvan Csomortani 5b01df91ac ad_rst: All the synchronization registers have to have ASYNC_REG TRUE 2018-08-14 17:54:14 +03:00
AndreiGrozav 4ddbb57749 daq3, fmcomms2/5: Cosmetic update only of the xdc files 2018-08-13 17:45:53 +03:00
AndreiGrozav c8fec4f70e daq3,fmcomms2/5 on zcu102: Fix warnings
DIFF_TERM is not supported in UltraScale devices.
2018-08-13 17:45:53 +03:00
Lars-Peter Clausen 5b94533cd0 adi_board.tcl: ad_ip_instance: Add support for specifying IP parameters
Add support for specifying a set of parameter value pairs when
instantiating an IP core to the ad_ip_instance command. This has the
convenience of not having to repeatedly call ad_ip_parameter with the name
of the core that got just created for each parameter that needs to be set.

It is also useful for cases where some parameters have mutually exclusive
values and both (or more) have to be set at the same time.

This also slightly speeds things up. Whenever a parameter is changed the
core needs to be updated and post configuration scripts might run. When
setting all parameters at the same time this only happens once instead of
once for each parameter.

For example the following sequence

  ad_ip_instance axi_dmac axi_ad9136_dma
  ad_ip_parameter axi_ad9136_dma CONFIG.DMA_TYPE_SRC 0
  ad_ip_parameter axi_ad9136_dma CONFIG.DMA_TYPE_DEST 1
  ad_ip_parameter axi_ad9136_dma CONFIG.DMA_DATA_WIDTH_SRC 64
  ad_ip_parameter axi_ad9136_dma CONFIG.DMA_DATA_WIDTH_DEST 256

can now be replaced with

  ad_ip_instance axi_dmac axi_ad9136_dma [list \
    DMA_TYPE_SRC 0 \
    DMA_TYPE_DEST 1 \
    DMA_DATA_WIDTH_SRC 64 \
    DMA_DATA_WIDTH_DEST 256 \
  ]

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-10 16:12:26 +02:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
Laszlo Nagy ec8a2cd9c5 adrv936x/ccbox_lvds: unconnected clock for ad9361 input protection
The 9361 protection circuits have no clocks connected,
export the clock from the block design for them.
2018-08-10 17:00:11 +03:00
Laszlo Nagy 05789e8978 adrv9009/adrv9371x/fmcomms2:Drop usage of ad_iobuf on non-bidirectional IOs
Some projects use the ad_iobuf on IOs that are not bidirectional
producing synthesis warnings.

The change fixes warnings like:
[Synth 8-6104] Input port 'gpio_bd_i' has an internal driver
[Synth 8-6104] Input port 'gpio_status' has an internal driver
2018-08-10 17:00:11 +03:00
Laszlo Nagy fa7c85a9eb all: Drive undriven input signals, complete interface
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top

fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]

The change excludes the generated system.v and Xilinx files.
2018-08-10 17:00:11 +03:00
Laszlo Nagy 059933b9c1 fmcadc4: Fix chip selects for ada4961 c,d channels
Chip selects for ada4961 C,D were always active since they were not
driven correctly.
2018-08-10 17:00:11 +03:00
Laszlo Nagy f0edafc4dc axi_spdif_rx: clear warning 2018-08-10 17:00:11 +03:00
Istvan Csomortani 495ba3891a ad_tdd_control: Register tdd_endof_frame
Register the tdd_endof_frame control signal to improve timing.
2018-08-10 14:06:38 +03:00
Istvan Csomortani 9eba3e8370 ad_tdd_control: Delete redundant reset from tdd_burst_counter logic
This way we can slightly improve timing.
2018-08-10 14:06:38 +03:00
Istvan Csomortani 375ccac072 ad_tdd_control: Switch '> 0' to '!= 0' to improve design 2018-08-10 14:06:38 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Istvan Csomortani 7e599ce09c ad_rst: Fix constraints for Intel designs 2018-08-09 10:26:18 +03:00
Istvan Csomortani e97d707f24 adi_tquest: Improve the timing report generation
If the analysis type is not defined the report_timing command will run
just a setup analysis.

Run an analysis report for all the four analysis type.
2018-08-08 15:09:19 +03:00
Istvan Csomortani 949073b012 ad_rst: Update SDC constraints of the module
The asynchronous set paths of the reset synchronization stage should be treated
as false-paths.
2018-08-07 13:35:24 +01:00
Istvan Csomortani 1e7f567e16 ad_rst: Initial value of the registers should be its default value
This patch will fix the following critical warning, generated by Quartus:

"Critical Warning (18061): Ignored Power-Up Level option on the following
registers
  Critical Warning (18010): Register ad_rst:i_core_rst_reg|rst_sync will power
  up to High File: ad_rst.v Line: 50"
2018-08-07 13:35:10 +01:00
Istvan Csomortani 66bf92ec9f axi_gpreg: Use the common ad_rst constraints 2018-08-06 21:24:41 +03:00
Istvan Csomortani 11071516d1 ad_rst: Update all the modules, which instantiate the ad_rst 2018-08-06 21:24:41 +03:00
Istvan Csomortani 472b12feb7 ad_rst: Update the reset synchronizer module
For a proper reset synchronization, the asynchronous reset signal should
be connected to the reset pins of the two synchronizer flop, and the
data input of the first flop should be connected to VCC.

In the first stage  we're synchronizing just the reset de-assertion, avoiding
the scenario when different parts of the design are reseting at different time,
causing unwanted behaviours.

In the second stage we're synchronizing the reset assertion.

The module expects an ACTIVE_HIGH input reset signal, and provides an ACTIVE_LOW
(rstn) and an ACTIVE_HIGH (rst) synchronized reset output signal.
2018-08-06 21:24:41 +03:00
AndreiGrozav 22ac59c4cf scripts/adi_project.tcl: Overrides the default individual msg limit to 2000 2018-08-06 18:18:13 +03:00
Istvan Csomortani c152b60137 ad_mem_asym: Improve the implementation of the asymmetric RAM
Because the read interface got a read enable port too, update all the
ad_mem_asym instances.
2018-08-06 17:29:05 +03:00
Istvan Csomortani e092149cbc adi_ip: Use 'associate_bus_interface' command to setup the clock and reset for s_axi 2018-08-06 10:14:48 +03:00
Istvan Csomortani 9441f00f5f adi_ip: Define the default driver value to 0 for unused ports 2018-08-06 10:14:48 +03:00
Istvan Csomortani 1388554faa adi_board.tcl: Update the VCC/GND instance generation
Just one VCC or GND xlconstant will be generated for each width. This
way we can avoid having a lot of xlconstant instances with the same
configuration.
2018-08-06 10:14:14 +03:00
Laszlo Nagy 085c0ed0da fmcadc5: remove SYSREF from IOB
The SYSREF for RX is generated internally,
disable the IOB attribute from it to avoid critical warnings.
2018-07-26 12:33:25 +03:00
Lars-Peter Clausen d5a1aa81e8 jesd204: Check lane error count in register map testbench
Assign a unique value to each lane's error count register and verify that
the correct value is returned for the right lane.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-24 15:20:28 +02:00
Lars-Peter Clausen b2ed915fbc jesd204: Fix RX regmap testbench version ID
The RX register map testbench currently fails because the expected value
for the version register was not updated, when the version was incremented.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-24 15:20:28 +02:00
Lars-Peter Clausen 57a5baad33 jesd204: Fix loopback testbench
The loopback testbench currently fails, because the cfg_links_disable signal is not connected to the RX side of the link.

Fix this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-24 15:20:28 +02:00
AndreiGrozav 74288cf9cb axi_hdmi_tx: Added INTERFACE parameter for selecting the interface type
Update all carriers/projects bd for configurable video interface:
- common zc702, zc706, zed
- adrv9361z7035/ccfmc_lvds
- imageon
2018-07-24 15:56:22 +03:00
Laszlo Nagy 0caea39bad jesd204_rx/tx: make SYSREF IOB placement optional
In case when the SYSREF is connected to an FPGA IO which has a limitation
on the IOB register IN_FF clock line and the required ref clock is high
we can't use the IOB registers.
e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz;

If IOB is used in this case a pulse width violation is reported.

This change makes the IOB placement selectable in such case or
for targets which don't require class 1 operation.
2018-07-24 09:16:24 +03:00
Laszlo Nagy 4d8008e64c axi_dmac: fix address width detection
The round function from tcl is a rounding to nearest. Using it in address
width calculation produces incorrect values.
e.g.
 round(log(0xAF000000)/log(2)) will produce 31 instead of 32

The fix is to replace the rounding function with ceiling that guarantees
rounding up.
2018-07-20 18:12:24 +03:00
AndreiGrozav 235636a337 fmcomms5_zc702: Enable AXI_SLICE for the DMA
This will increase the timing margin for the design
2018-07-18 18:19:30 +03:00
AndreiGrozav 77db4c200c axi_ad9371: Increase dds quality 2018-07-18 18:19:30 +03:00
AndreiGrozav 89692b40b5 axi_ad9144: Increase dds quality 2018-07-18 18:19:30 +03:00
AndreiGrozav 989fa6fd27 axi_ad9122: Increase dds quality 2018-07-18 18:19:30 +03:00
AndreiGrozav 6083d74857 axi_ad9739a: Use polynomial DDS 2018-07-18 18:19:30 +03:00
AndreiGrozav 79003c53db ad_dds: Fix synthesis updates
- remove reset logic
- add wait for dac valid logic
- rewrite sine concatenation on wires for different path width to
suppress warnings
- use computed atan LUT tables
2018-07-18 18:19:30 +03:00
AndreiGrozav 892febe68a ad_dds_2: Remove unused disable logic feature 2018-07-18 18:19:30 +03:00
AndreiGrozav 8a306ce96b axi_ad9162: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 8cd88150f1 axi_ad9152: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav a2d3c87aa5 axi_adrv9009: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 92f0e809b5 jesd204/ad_ip_jesd204_tpl_dac: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 528460371c axi_ad9963: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 92dbd75414 axi_ad9739a: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 25dbca7eed axi_ad9371: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 42abe0cf46 axi_ad9361: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00