Commit Graph

2235 Commits (04af519af87dcf293fb0bd14131738425a552c18)

Author SHA1 Message Date
Istvan Csomortani 04af519af8 axi_adxcvr: Re-indent ports 2019-03-21 14:30:39 +02:00
Istvan Csomortani 845c369c6b axi_adcvr: Add initial value for reg port definition 2019-03-21 14:30:39 +02:00
Istvan Csomortani 8996044978 axi_adxcvr: Fix warning related to up_es_reset
Fix the following warning:

WARNING: [Synth 8-2611] redeclaration of ANSI port up_es_reset is not allowed

Also make sure, that in all configurations, the register has a diver.
2019-03-21 14:30:39 +02:00
Istvan Csomortani 59713f96ab util_tdd_sync: Fix util_pulse_gen instantiation 2019-03-21 07:28:18 +00:00
Istvan Csomortani a337774dfa ad_ip_jesd204_tpl_dac: Add 8 bit resolution support 2019-03-20 15:51:28 +02:00
Istvan Csomortani e3e96177c4 ad_ip_jesd204_tpl_adc: Add 8 bit resolution support
Add support for 8 bit resolution for the transport layer.

Fix parameter BITS_PER_SAMPLES propagation to all the internal modules, in
several cases this variable was hard coded to 16.
2019-03-20 15:51:28 +02:00
Istvan Csomortani ac4d78b95d ad_datafmt: Add support for 8 bit data width 2019-03-20 15:51:28 +02:00
sarpadi 2f68c546f1
Merge pull request #244 from analogdevicesinc/axi_i2s_adi_update
axi_i2s_adi: fixed xdc
2019-03-20 13:42:23 +02:00
Istvan Csomortani 0e7b38ebcf axi_pulse_gen: Initial commit
The axi_pulse_gen is a generic PWM generator, which can be configured
through an AXI Memory Mapped interface.

The current register map look like follows:

  0x00 - VERSION
  0x04 - ID
  0x08 - SCRATCH
  0x0C - IDENTIFICATION - 0x504c5347 which stands for 'PLSG' in ASCII
  0x10 - CONFIGURATION - contains reset and load bits
  0x14 - PULSE_PERIOD
  0x18 - PULSE_WIDTH

Also update all the other modules, which instantiate the util_pulse_gen.
2019-03-20 08:21:22 +00:00
Istvan Csomortani f15ed8475e util_pulse_gen: Change the counter to a down-counter
To prevent the case, when after an invalid configuration, the generated
output PWM signal is constant HIGH, change the counter to a
down-counter. In this way the pulse will be placed at the end of the
PWM period, and if the configured width value is higher than the
configured period the output signal will be constant LOW.
2019-03-20 08:21:08 +00:00
Istvan Csomortani 2d7b189ba3 util_pulse_gen: Add an input configuration port for pulse width attribute 2019-03-19 16:33:10 +00:00
Sergiu.Arpadi 0e333bf5ae axi_i2s_adi: fixed xdc
ip now sets the xdc to late so that the timing constraints are set in the correct context
2019-03-18 13:58:28 +00:00
Laszlo Nagy a3ce8c5ca6 axi_rd_wr_combiner: Add rlast to the AXI MM interface
The DMAC is relying on the rlast signal that marks the end of a burst.
2019-02-21 17:09:53 +02:00
Laszlo Nagy c10c4d4f5e up_dac_common: fix address decoding
Patch the typo introduced in a previous commit while attempting the
address space reduction.
2019-02-19 15:38:45 +02:00
AndreiGrozav 1c8172de7f axi_adc_trigger: Cosmetic update
Use localparam DW = 15 - SIGN_BITS
2019-02-18 13:39:24 +02:00
AndreiGrozav 44e20d095c axi_adc_trigger: Fix triggering jitter effect 2019-02-18 13:39:24 +02:00
AndreiGrozav 2ec578c216 axi_hdmi_tx: Update file sources for Intel designs 2019-02-12 10:43:46 +02:00
AndreiGrozav fae4d478d4 ad_csc: Generalize for CrYCB 2 RGB conversion 2019-02-12 10:43:46 +02:00
AndreiGrozav 74eacc2369 ad_csc(RGB2CrYCb): use signed multiplication. 2019-02-12 10:43:46 +02:00
AndreiGrozav 265781f29a axi_hdmi: Let the tools assign the csc resources
Write code to pipeline data path for better DSP utilization on the
color space conversion.
In the old method the addition operations were performed outside the
DSPs
2019-02-12 10:43:46 +02:00
Adrian Costina 47f7894881 util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4) 2019-02-11 17:20:08 +02:00
Laszlo Nagy ca1ba6a6fe axi_ad9144/axi_ad9152: patch up_tpl_common dependency 2019-02-01 08:28:28 +00:00
Istvan Csomortani b2d86bab47 util_axis_fifo: Fix the FIFO level generation in ASYNC mode
The FIFO functions in 'first fall through' mode, adjust the fifo level
generation so it take into account the valid data which sits on the bus,
waiting for ready, too.
2019-01-29 11:38:28 +02:00
Laszlo Nagy b221718bfe jesd204:up_tpl_common: reduce and move address space
Limit the tpl register space to 128 locations mapped to 128-255 in the COMMON_ID segment.
2019-01-23 17:44:33 +02:00
Laszlo Nagy 93df754800 up_adc_common/up_dac_common: reduce address space to half
Limit the adc/dac common space to 128 registers mapped 0-127 in the COMMON_ID segment.
2019-01-23 17:44:33 +02:00
Laszlo Nagy cf593d5a40 jesd204_tpl: addresses cleanup
The TPL has an address space of 12 bits while the legacy subcomponents
have 16 bits. Update the module for a better readability.
2019-01-23 17:44:33 +02:00
Laszlo Nagy 560e9b9e52 jesd204_tpl: expose jesd parameters to software
This change will allow software to identify the available JESD framer/deframer
settings from the transport layer.
2019-01-23 17:44:33 +02:00
Laszlo Nagy c6c825c90a jesd204/tb: support for ModelSim and Xsim
Adding support for ModelSim and Vivado Xsim.

Usage:
  export SIMULATOR=modelsim
    or
  export SIMULATOR=xsim
2019-01-21 10:33:30 +02:00
Adrian Costina b052e40637 ad_ip_jesd204_tpl: Fix chanmax reporting for both ADC and DAC 2019-01-16 11:40:17 +02:00
Laszlo Nagy 3d7a376f8b Makefile: update makefiles 2018-12-21 17:32:48 +02:00
Laszlo Nagy a65bafb056 ad_ip_jesd204_tpl_dac: expose OCTETS_PER_BEAT parameter 2018-12-21 17:32:48 +02:00
Laszlo Nagy fc74201c88 axi_dmac: patch version checking
Current implementation does not supports updated versions of Vivado
e.g. 2017.4.1 or 2018.2.1

This fix ignores the update number from the version checking.
2018-12-20 10:32:48 +02:00
Laszlo Nagy 032bf7c3ef jesd204: create wrappers around TPLs in BD 2018-12-04 14:02:22 +02:00
Laszlo Nagy 8bce4c5b0a jesd204_tpl: update address widths of TPL instances 2018-12-04 14:02:22 +02:00
Laszlo Nagy 57f83f86ab jesd204_tpl: reduce address width of TPLs
Registers from this component can fit in the 2k address range.
Since Vivado's minimal address range is 4k, use that instead.
This will allow placing the independent TPLs to base addresses
that mach the addresses from the monolithic blocks ensuring no software
intervention.
2018-12-04 14:02:22 +02:00
Laszlo Nagy 26c0121f4d ud_ip_jesd204_tpl_adc: update TPL instances 2018-12-04 14:02:22 +02:00
Laszlo Nagy 9c51f7f975 ad_ip_jesd204_tpl_adc: make core more generic 2018-12-04 14:02:22 +02:00
Laszlo Nagy f41806c1be common/ad_xcvr_rx_if: make core more generic 2018-12-04 14:02:22 +02:00
Laszlo Nagy 41413a8ffe ad_ip_jesd204_tpl_adc: make PN monitor more generic 2018-12-04 14:02:22 +02:00
Laszlo Nagy c34a304d3c ad_ip_jesd204_tpl_adc: expose core in IP catalog 2018-12-04 14:02:22 +02:00
Lars-Peter Clausen 804c57aabc axi_dmac: Remove length alignment requirement for MM interfaces
The DMAC has the requirement that the length of the transfer is aligned to
the widest interface width. E.g. if the widest interface is 256 bit or 32
bytes the length of the transfer needs to be a multiple of 32.

This restriction can be relaxed for the memory mapped interfaces. This is
done by partially ignoring data of a beat from/to the MM interface.

For write access the stb bits are used to mask out bytes that do not
contain valid data.

For read access a full beat is read but part of the data is discarded. This
works fine as long as the read access is side effect free. I.e. this method
should not be used to access data from memory mapped peripherals like a
FIFO.

This means that for example the length alignment requirement of a DMA
configured for a 64-bit memory and a 16-bit streaming interface is now only
2 bytes instead of 8 bytes as before.

Note that the address alignment requirement is not affected by this. The
address still needs to be aligned to the width of the MM interface that it
belongs to.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-30 23:41:49 +02:00
Lars-Peter Clausen 7986310fa0 axi_dmac: burst_memory: Add support for using asymmetric memory
FPGAs support different widths for the read and write port of the block
SRAM cells. The DMAC can make use of this feature when the source and
destination interface have a different width to up-size/down-size the data
bus.

Using memory cells with asymmetric port width consumes the same amount of
SRAM cells, but allows to bypass the re-size blocks inside the DMAC that
are otherwise used for up- and down-sizing. This reduces overall resource
usage and can improve timing.

If the ratio between the destination and source port is too larger to be
handled by SRAM alone the SRAM block will be configured to do partial up-
or down-sizing and a resize block will be inserted to take care of the
remaining up-/down-sizing. E.g. if a 256-bit interface is connected to a
32-bit interface the SRAM will be used to do an initial resizing of 256 bit
to 64 bit and a resize block will be used to do the remaining resizing from
64 bit to 32 bit.

Currently this feature is disabled for Intel FPGAs since Quartus does not
properly infer a block RAM with different read and write port widths from
the current ad_asym_mem module. Once that has been resolved support for
asymmetric memories can also be enabled in the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-30 23:41:49 +02:00
Lars-Peter Clausen c8900eb8ab axi_dmac: burst_memory: Move src valid bytes resizing to resize_src module
The handling of the src_data_valid_bytes signal and its related signal is
tightly coupled to the behavior of the resize_src module. The code that
handles it makes assumptions about the internal behavior of the resize_src
module.

Move the handling of the src_data_valid_bytes signal when upsizing the data
bus into the resize_src module so that all the code that is related is in
the same place and the code outside of the module does not have to care
about the internals.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-30 23:41:49 +02:00
Lars-Peter Clausen 00090b1899 axi_dmac: burst_memory: Consider DMA_LENGTH_ALIGN
The DMA_LENGTH_ALIGN LSBs of all length For the most part the tools are
able to deduce this using constant propagation.

But this propagation does not work across the asynchronous meta data FIFO
in the burst memory module.

Add a DMA_LENGTH_ALIGN parameter to the burst_memory module which is used
to explicitly keep the LSBs of length registers on the destination side
fixed at 1'b1. This reduces resource use and improves timing by allowing
better constant propagation and unused logic elimination.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-30 23:41:49 +02:00
Lars-Peter Clausen 34e89b9e39 axi_dmac: burst_memory: Reset beat counter at the end of each burst
This simplifies the burst length in the response manager significantly
while not costing much extra resources in the burst memory.

This change will also enable other future improvements.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-30 23:41:49 +02:00
Lars-Peter Clausen 764f31463e axi_dmac: tb: Allow testing asymmetric interface widths
One of the major features of the DMAC is being able to handle non matching
interface widths for the destination and source side.

Currently the test benches only support the case where the width for the
source and the destination side are the same. Extend them so that it is
possible to also test and verify setups where the width is not the same.

To accomplish this each byte memory location is treated as if it contained
the lower 8 bytes of its address. And then the written/read data is
compared to the expected data based on that.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-30 23:41:49 +02:00
Lars-Peter Clausen 29e6bbde88 altera: adi_jesd204: Add support for more than 6 transmit lanes
On Arria10 there are 6 transceivers in a single bank. If more than 6
transceivers are used these will end up in multiple banks.

The ATX PLL can directly connect to the transceivers in the same bank
through the 1x clock network. To connect to transceivers in another bank it
has to go through a master clock generation block (MCGB) and the xN clock
network.

Add support for instantiating the MCGB if more than 6 lanes are used. In
this case the first 6 transceivers will still have a direct connection to
the PLL while all other transceivers will be clocked by the MCGB.

Note that this requires that the first 6 transceivers are all in the same
bank.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:37 +02:00
Lars-Peter Clausen a0309e3e3a Remove old util_cpack and util_upack core
All projects have been updated to use the new pack/unpack infrastructure.
The old util_cpack and util_upack cores are now unused an can be removed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 0a30cdbf99 Add util_cpack2 core
The util_cpack2 core is similar to the util_upack core. It packs, or
interleaves, a data from multiple ports into a single data. Ports can
optionally be enabled or disabled.

On the input side the cpack2 core uses a multi-port FIFO interface. There
is a single data write signal (fifo_wr_en) for all ports. But each port can
be individually enabled or disabled using the enable signals.

On the output side the cpack2 core uses a single port FIFO interface. When
data is available on the output interface the data write signal
(packed_fifo_wr_en). Data on the packed_fifo_wr_data signal is only valid
when packed_fifo_wr_en is asserted. At other times the content is
undefined. The cpack2 core offers no back-pressure. If data is not consumed
when it is made available it will be lost.

Data from the input ports is accumulated inside the cpack2 core and if
enough data is available to produce a full output vector the data is
forwarded.

This core is build using the common pack infrastructure. The core that is
specific to the cpack2 core is mainly only responsible for generating the
control signals for the external interfaces.

The core is accompanied by a test bench that verifies correct behavior for
all possible combinations of enable masks.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 90540bf447 Add util_upack2 core
The util_upack2 core is similar to the util_upack core. It unpacks, or
deinterleaves, a data stream onto multiple ports.

The upack2 core uses a streaming AXI interface for its data source instead
of a FIFO interface like the upack core uses.

On the output side the upack2 core uses a multi-port FIFO interface. There
is a single data request signal (fifo_rd_en) for all ports. But each port
can be individually enabled or disabled using the enable signals.

This modified architecture allows the upack2 core to better generate the
valid and underflow control signals to indicate whether data is available
in a response to a data request.

If fifo_rd_en is asserted and data is available the fifo_rd_valid signal
are asserted in the following clock cycle. The enabled fifo_rd_data ports
will be contain valid data during the same clock cycle as fifo_rd_valid is
asserted. During other clock cycles the output data is undefined. On
disabled ports the data is always undefined.

If no data is available instead the fifo_rd_underflow signal is asserted in
the following clock cycle and the output of all fifo_rd_data ports is
undefined.

This core is build using the common pack infrastructure. The core that is
specific to the upack2 core is mainly only responsible for generating the
control signals for the external interfaces.

The core is accompanied by a test bench that verifies correct behavior for
all possible combinations of enable masks.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00