4 Commits (04a4001dbaa0b12260710c6fd1a07e4a6b95c561)

Author	SHA1	Message	Date
Istvan Csomortani	ac2e5a9dac	constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.	2017-02-24 13:43:32 +02:00
Istvan Csomortani	1fce57f6c3	axi_dacfifo: Redesign the bypass functionality	2017-02-23 17:32:31 +02:00
Istvan Csomortani	e3ac341aad	axi_dacfifo: Fix constraints	2017-02-21 14:45:18 +02:00
Istvan Csomortani	3b0c1e02fc	axi_dacfifo: Move IP to library/xilinx	2016-09-15 11:38:16 +03:00