Depending on whether the core is configured for AXI4 or AXI3 mode the width
of the awlen/arlen signal is either 8 or 4 bit. At the moment this is only
considered in top-level module and all other modules use 8 bit internally.
This causes warnings about truncated signals in AXI3 mode, to resolve this
forward the width of the signal through the core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a register to the AXI DMAC register map which functions has a
identification register. The register contains the unique value of "DMAC"
(0x444d4143) and allows software to identify whether the peripheral mapped
at a certain address is an axi_dmac peripheral.
This is useful for detecting cases where the specified address contains an
error or is incorrect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The address width for the AXI-Lite configuration bus for the core is only
14 bit. Remove the upper unused bits from the public interface.
This allows infrastructure code to know about this and it might be able to
perform optimizations of the interconnect based on this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Move the clock and reset signals of the m_axi_src interface next to the
other signals in the module definition.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The dummy a{r,w}len fields should have the same width as the real a{w,r}len
fields in order to not break auto AXI bus version detection.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We can remove the Altera toplevel wrapper if we switch the axi4 control bus
to axi4lite and add the few missing signals that are required by the Altera
interconnect to both the control and the data buses.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The read data also becomes available only with a delay of one clock cycle,
sending the ack too early will result in bogus register reads.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Vivado doesn't handle the case where we use symbolic constants for the default
value properly, so update this to use plain integers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Lars-Peter Clausen
Istvan Csomortani
AndreiGrozav
Rejeesh Kutty
Adrian Costina