Commit Graph

188 Commits (03e744f0f1b697a3397a8269d02a4777e5bac33d)

Author SHA1 Message Date
Lars-Peter Clausen f0655e63a6 avl_adxcvr: Derive PLL and core clock frequency from lane rate
The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.

Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Lars-Peter Clausen debca3a153 fmcjesdadc1: vc707: Remove unsed mb_intrs signal
The mb_intrs signal is never driven, it is a leftover of an earlier version
of the file, remove it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:38:25 +02:00
Lars-Peter Clausen 0360e8587e Connect JESD204 interrupts
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
Rejeesh Kutty 3fb5408acc fmcjesdadc1/a10gx- fix sysref, lvds io and such 2017-06-15 13:57:21 -04:00
Rejeesh Kutty 6ec9eab7b9 fmcjesdadc1/a10soc- fix sysref, lvds io and such 2017-06-15 13:57:21 -04:00
Rejeesh Kutty ef290ef484 hdlmake.pl updates 2017-06-15 11:42:44 -04:00
Rejeesh Kutty e33e6a84f4 a5gt/a5soc - removed 2017-06-15 11:41:28 -04:00
Rejeesh Kutty 7ac083b932 fmcjesdadc1/a10soc- sysref fixes 2017-06-15 10:15:59 -04:00
Rejeesh Kutty 004aee930b fmcjesdadc1/a10gx- fix sysref, gpio connections 2017-06-14 14:40:23 -04:00
Rejeesh Kutty dba419239b hdlmake.pl updates 2017-06-14 10:41:14 -04:00
Rejeesh Kutty 3299d244fe fmcjesdadc1: a10gx/a10soc 2017-06-14 10:39:57 -04:00
Rejeesh Kutty 38c708d4d0 fmcjesdadc1: a10gx/a10soc 2017-06-14 10:39:38 -04:00
Rejeesh Kutty 051c1d6644 fmcjesdadc1: a10soc 2017-06-13 15:00:22 -04:00
Rejeesh Kutty c1bc1259a7 fmcjesdadc1: a10gx 2017-06-13 12:39:45 -04:00
Rejeesh Kutty 3f3ea5f99a hdlmake.pl- updates 2017-06-13 09:55:08 -04:00
Rejeesh Kutty 0eacde9158 fmcjesdadc1/a5soc- alt 16.1 updates 2017-06-13 09:54:01 -04:00
Rejeesh Kutty 6decba3c3b hdlmake.pl updates 2017-06-09 16:23:17 -04:00
Rejeesh Kutty 74f9a99655 fmcjesdadc1/a5gt- altera 16.1 updates 2017-06-09 16:20:49 -04:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 4c998d1e18 make: Update make files 2017-05-25 15:12:17 +03:00
Lars-Peter Clausen d4c9f1e9f1 fmcjesdac1: Convert to ADI JESD204
Convert the FMCJESDADC1 project to the ADI JESD204 link layer core. The
change is very straight forward, but a matching change on the software side
is required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 01aea161fa Create CDC helper library
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Istvan Csomortani 0442e7d404 util_adxcvr: Fix parameter setup at instantiation
If a parameter value is defined as a string binary (e.g. "001001000000"),
it can confuse the tool, and the value may be used as a decimal number.
To prevent this issue and to improve readability converting all the binary
constants into hexadecimal.
2017-04-27 15:35:39 +03:00
Istvan Csomortani 95249d2165 fmcjesdadc1: Update IP instantiations 2017-04-21 15:08:16 +03:00
Adrian Costina 942d69a30c Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Adrian Costina 968d94603e fmcjesdadc1: Update xcvr configuration to the default one used for this board 2017-03-23 11:31:00 +02:00
AndreiGrozav e736504e0f fmcjesdadc1, usdrx1: Using the same clock in rx_data path 2017-03-10 14:26:51 +02:00
AndreiGrozav 7e5d8664ad fmcjesdadc1_a5gt: rx_data pins are all associated to the same clock 2017-03-09 08:57:03 +02:00
Istvan Csomortani ac2e5a9dac constraints: Update constraints
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
Rejeesh Kutty cb3d1883bc fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers 2017-02-17 15:21:33 -05:00
Istvan Csomortani 5fa6dba333 Make: Update Makefiles 2017-02-10 16:32:58 +02:00
Rejeesh Kutty 35f660fe06 fmcjesdadc1/vc707- constraint clean-up 2017-02-02 15:05:49 -05:00
Istvan Csomortani f003b5b35a fmcjesdadc1: Reduce SYSREF period 2017-01-12 16:10:45 +02:00
Rejeesh Kutty 37d54bb984 fmcjesdadc1/a5gt- max delay fit only 2017-01-04 16:04:19 -05:00
Rejeesh Kutty 8b74e911b8 fmcjesdadc1/a5gt- qr to ddio max delay 2017-01-04 14:10:44 -05:00
Rejeesh Kutty 14ded4f123 fmcjeadadc1/a5soc- ad_sysref_gen updates 2016-12-22 15:59:45 -05:00
Rejeesh Kutty b089173b4c fmcjesdadc1/a5soc- cpu clock is 50m for a5gt also 2016-12-22 14:14:21 -05:00
Rejeesh Kutty 18660c7ab4 fmcjesdadc1/a5gt: ddr3 use ip constraints 2016-12-22 14:14:21 -05:00
Rejeesh Kutty 2bea337aa2 fmcjesdadc1/a5gt- use 50m-mem-cpu-clk 2016-12-22 14:14:21 -05:00
Rejeesh Kutty 5d683943ab fmcjesdadc1/a5gt- remove ad-sysref-gen-pack 2016-12-22 14:14:21 -05:00
Rejeesh Kutty f1168f9e29 fmcjesdadc1/a5gt- use xilinx setup 2-dma 2016-12-22 14:14:21 -05:00
Rejeesh Kutty 4a783d523d projects/altera* - default & common qsys commands 2016-12-20 16:27:44 -05:00
Istvan Csomortani 1156aeac16 ad_sysref_gen: Update SYSREF related constraints 2016-12-19 18:07:05 +02:00
Istvan Csomortani da7f4608a8 fmcjesdadc1/usdrx1: Clean up the mess
Delete accidentally commited generated files.
2016-12-19 15:35:20 +00:00