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3051 Commits (0208335ef3e4748dbacfd55a4058d48338d5ad4e)

Author SHA1 Message Date
Adrian Costina d0a8b4a63c kc705,common: Mem_interconnect maximize performance 
For FMCOMMS1, when both the ADC and DAC DMAs are active, the system was
unstable. With this fix, it the system seems to be stable.
 2014-04-03 15:59:33 +03:00
Rejeesh Kutty f8f2684b7e up_gt: eyescan delay bug fix 2014-04-02 16:45:41 -04:00
Rejeesh Kutty e85153b5dd altera hal version 2014-04-01 21:12:11 -04:00
Rejeesh Kutty 80e5051894 axi_jesd_gt: initial checkin 2014-04-01 15:14:28 -04:00
Rejeesh Kutty 2472d61daf ad_gt_es: status asserted early for latency 2014-04-01 15:06:51 -04:00
Rejeesh Kutty 04df908fbf altera-fmcjesdadc1 initial checkin 2014-04-01 12:01:57 -04:00
Rejeesh Kutty 0d678b89ed altera a5gt fmcjesdadc1 setup 2014-04-01 11:46:37 -04:00
Rejeesh Kutty 724bd70a06 altera additions and replacements 2014-04-01 11:18:10 -04:00
Istvan Csomortani 8deb36ce08 adi_board.tcl: All procedures works on Zynq/Microblaze 
General patch for the integration procedures. Tested on kc705 and
	zed.
 2014-04-01 16:19:24 +03:00
ATofan 9676146725 FMCOMMS2 AC701 Project 
Not tested - must program Vadj on board
 2014-04-01 15:35:44 +03:00
ATofan e597467447 FMCOMMS2 VC707 Project 2014-04-01 15:34:29 +03:00
ATofan 814b0d72d6 Modified Reset signals for FMCOMMS2 base design 
Made all resets the same (sys_100m_resetn)
 2014-04-01 15:32:48 +03:00
Istvan Csomortani fbafaa8507 MicroBlaze base system: Fix a few net names 
Every interconnect interface net name follows the convention:
	<interconnect name>_<interface name>
	No changes in logic or any connection!
 2014-04-01 10:40:35 +03:00
Adrian Costina f0b8b8f6c0 FMCOMMS1: KC705 updated system_top and constraints 
Needed to be compatible with the latest common file
 2014-03-31 17:49:10 +03:00
Adrian Costina 14b82c03dd FMCOMMS1: Several modifications in the base design 
Corrected the ADC/DAC interrupt location for microblaze systems
Removed the ILA clock generation from sys_audio_clkgen and created a
separate clock generator
All system is reset from the same source
 2014-03-31 17:44:57 +03:00
Adrian Costina a881557645 base_design: Fixed AC701 and VC707 contstraints 
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
 2014-03-31 17:38:20 +03:00
Rejeesh Kutty 25f416e46f dds output is reset if disabled 2014-03-31 10:01:49 -04:00
Istvan Csomortani 4ef88a3bed adi_board.tcl : Patch for adi_spi_core process 
- Fix indentation
	- Pacth for adi_spi_core process
 2014-03-31 16:41:07 +03:00
Istvan Csomortani 7f4f200fce Project scripts: Initial check in of adi_board.tcl 
The script contains integration tcl processes.
 2014-03-26 19:08:56 +02:00
Istvan Csomortani f9a67371c0 Zynq Base System: Reset is synchronized to lowest system clock 
System reset (sys_100m_reset) is synchronized to lowest system
	clock (FCLK0), via a Processor System Reset module
 2014-03-26 17:58:14 +02:00
Rejeesh Kutty d3d26e1220 lower the address space requirements 2014-03-26 11:03:45 -04:00
Lars-Peter Clausen 9b4539b7c2 axi_dmac: Add option to configure the FIFO size 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-26 12:51:35 +01:00
Adrian Costina ad5ef35b48 fmcomms1: modified *_bd.tcl files formatting 2014-03-26 12:05:42 +02:00
Lars-Peter Clausen ca7a70650d axi_dmac: Delay up_ack by one clock cycle 
The read data also becomes available only with a delay of one clock cycle,
sending the ack too early will result in bogus register reads.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-25 14:35:52 +01:00
Adrian Costina 8f7d4c9b26 FMCOMMS1: Fixed typo in common/fmcomms1_bd.tcl 2014-03-25 14:34:55 +02:00
Istvan Csomortani 0f10623be4 AC701/VC707: Define common variables 
Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
 2014-03-25 14:24:51 +02:00
Lars-Peter Clausen b3657b77cb util_sync_reset: Fix polarity of the sync_resetn signal 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-25 13:03:12 +01:00
Lars-Peter Clausen a230e6505a axi_dmac: Add option to configure AXI standard 2014-03-25 12:47:27 +01:00
Lars-Peter Clausen d0e26899a4 Add util_sync_reset helper module 
This helper module can be used to make sure that a reset signal is de-asserted
synchronously to a clock signal. This is e.g. required by the AXI spec.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-24 22:43:01 +01:00
Rejeesh Kutty ef960a29c7 altera files 2014-03-24 13:27:27 -04:00
Adrian Costina 2070c66b87 Fmcomms1: Initial commit for KC705 
Modified common project so it can be compatible for both ARM and
Microblaze based systems.
 2014-03-24 16:52:24 +02:00
Istvan Csomortani aa7b0bb4dd VC707 basesys: General fixes, actual status: working 
- Add an auxiliary cpu interconnect
	- Add an auxiliary interrupt concatenation module
	- Add new MIG file, current frequency of the DDR interface is 100
	  Mhz
	- Memory interconnect optimisation strategy is 'Maximize
	  Performance'
 2014-03-24 13:07:48 +02:00
Istvan Csomortani b94acf78aa AC701 bases sys: Add an auxiliary cpu interconnect 
- Add an auxiliary cpu interconnect, the KC705 base system was
	  used as reference
	- Base system is tested and working
 2014-03-24 13:01:52 +02:00
Istvan Csomortani 792e8a208d KC705 base system: Make a few cosmetic changes 2014-03-24 12:55:37 +02:00
ATofan f8c1179bc1 FMCOMMS2 KC705 Project. 
Added the files required for the FMCOMMS2 KC705 project.
Both DMA and DDS work.
 2014-03-24 11:48:52 +02:00
Istvan Csomortani 8a08031dce AC701: Modify interrupt concatenation 
- Interrupt concatenation is the same as in case of KC705
 2014-03-24 10:20:56 +02:00
Istvan Csomortani 13b4dd07d0 KC705 base system: Modify interrupt concatanation 
- Add an aditional interrupt input net for the sys_concat_aux_intc
	  module
 2014-03-21 14:45:18 +02:00
Istvan Csomortani c6143dbfaf KC705 base system: Delete trailing whitespaces. 2014-03-21 14:42:27 +02:00
ATofan 31a1ff384d FMCOMMS2 Base Design tcl modified 
Added support for both Zynq and MicroBlaze projects
 2014-03-21 09:57:52 +02:00
Adrian Costina 551319a670 Modified data mover to improve timing 2014-03-20 18:22:18 +02:00
Istvan Csomortani 3a0d1282b7 Fix the remaining issues 
- Swap the IO locations of ports vsync and hsync
	- Change the mem_interconnect optimization strategy to Maximize
	  Performance
 2014-03-20 14:36:01 +02:00
Adrian Costina 698e9f4757 Added phys_opt_design step for fixing timing 
The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step
is part of the implmentation flow, with the Explore argument.
"This step performs physical optimizations such as timing-driven
replicaiton of high fanouts nets to improve timing results"
 2014-03-19 16:42:44 +02:00
Lars-Peter Clausen e373b85954 axi_dmac: Fix Vivado warnings 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-18 20:59:13 +01:00
Lars-Peter Clausen 29d590c951 axi_dmac: response_generator: Do not generate responses during ID sync 
During an ID sync the request_id might increment, we should not generate a
response in this case. Since the ID sync only happens when the core is disabled
check that the core is enabled before generating a response.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-18 19:12:13 +01:00
Lars-Peter Clausen df1c4f0786 axi_dmac: data_mover: Improve timing 
The pending_burst signal and the expression id != request_id are almost
identical. pending_burst goes high with a delay of one clock cycle, but the
important thing is that it goes low on the same clock cycle as the expression.
By using pending_burst here instead of 'id != request_id' we can reduce the
fanout of the 'id' register and improve the timing of the core.
 2014-03-18 19:06:26 +01:00
Istvan Csomortani 7cdab9b5b0 Change the internal clock generator to Clock Wizard 
- Using a Clock Wizard Module, in place of the DDR Controler's MMCM for internal clock
	  generation.
 2014-03-18 17:24:45 +02:00
ATofan 9d65071235 Merge branch 'master' of https://github.com/analogdevicesinc/hdl 2014-03-18 15:30:29 +02:00
ATofan 2c898bf3a2 Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project 
ZC706 runs rx_clk at 250 MHz.
ZC702 and ZED run rx_clk at 200 MHz due to slower fabric.
The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly.
Both DDS and DMA mode work.
 2014-03-18 15:27:42 +02:00
Rejeesh Kutty f3c503cfb8 Merge branch 'master' of github.com:analogdevicesinc/hdl 2014-03-17 21:33:13 -04:00
Rejeesh Kutty dc44703cf1 zynq/non-zynq: identical signal names and instances 2014-03-17 17:02:03 -04:00